US5828106A
Expired / Lapsed
US
⏱️ 0.0 years remaining
ESD tolerated SOI device
Assignee: Fujitsu Semiconductor Ltd
•
Filing: 1997-08-20
•
Granted: 1998-10-27
•
Expires: 2017-08-20
Abstract
Abstract A semiconductor-on-insulator (SOI) type semiconductor device with an enhanced electrostatic discharge (ESD) tolerance having a semiconductor layer on an insulating support substrate, comprising a pair of voltage supply lines formed on the semiconductor layer, a pair of low resistivity semiconductor regions connected to said pair of source supplying lines and disposed within the layer, and a dielectric region disposed between said pair of low resistivity semiconductor regions; wherein said pair of low resistivity semiconductor regions form a capacitor.
Inventors
- 👤 Noriaki Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:12
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/201; H10D89/00; H10D89/60; H10D89/601
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
144 words
A semiconductor-on-insulator (SOI) type semiconductor device comprising: a support substrate having a top insulating layer, the insulating layer having a first surface; semiconductor regions embedded in said insulating layer, and each having a second surface which forms a copolanar surface with said first surface; a pair of voltage supply lines formed on said copolanar surface; a plurality of active semiconductor regions among said semiconductor regions, constituting transistors of an integrated circuitry; a pair of low resistivity semiconductor regions among said semiconductor regions, connected with said pair of voltage supply lines, disposed at a same level and exposed at said coplanar surface, and dielectrically isolated from each other; and a dielectric region formed of said insulating layer, disposed between said pair of low resistivity semiconductor regions; wherein said pair of low resistivity semiconductor regions solely form a capacitor and do not constitute said integrated circuitry.
Claim 2
Dependent Claim
144 words
A semiconductor-on-insulator (SOI) type semiconductor device comprising: a support substrate having a top insulating layer, the insulating layer having a first surface; semiconductor regions embedded in said insulating layer, and each having a second surface which forms a copolanar surface with said first surface; a pair of voltage supply lines formed on said copolanar surface; a plurality of active semiconductor regions among said semiconductor regions, constituting transistors of an integrated circuitry; a pair of low resistivity semiconductor regions among said semiconductor regions, connected with said pair of voltage supply lines, disposed at a same level and exposed at said coplanar surface, and dielectrically isolated from each other; and a dielectric region formed of said insulating layer, disposed between said pair of low resistivity semiconductor regions; wherein said pair of low resistivity semiconductor regions solely form a capacitor and do not constitute said integrated circuitry.
Claim 3
Dependent Claim
31 words
An SOI-type semiconductor device according to claim 1, wherein said support substrate comprises a semiconductor substrate, and an insulating layer formed on the semiconductor substrate and continuing to said dielectric region.
Claim 4
Dependent Claim
34 words
An SOI-type semiconductor device according to claim 2, wherein said pair of low resistivity semiconductor regions are disposed facing to each other on their side surfaces through said dielectric region, thereby forming a capacitance.
Claim 5
Dependent Claim
31 words
An SOI-type semiconductor device according to claim 3, wherein a plurality of said pair of low resistivity semiconductor regions is provided and connected to a pair of common voltage supply lines.
Claim 6
Dependent Claim
37 words
An SOI-type semiconductor device according to claim 3, wherein said pair of low resistivity semiconductor regions have such a shape, when projected on a surface of the support substrate, that the regions comprise parts of interdigital engagement.
Claim 7
Dependent Claim
42 words
An SOI-type semiconductor device according to claim 3, wherein peripheries of said pair of low resistivity semiconductor regions do not have a horizontal cross section in the layering direction having a bent part having an angle equal to or less than 90°.
Claim 8
Dependent Claim
31 words
An SOI-type semiconductor device according to claim 3, wherein said pair of low resistivity semiconductor regions have such a configuration that one of the regions surrounds the other of the regions.
Claim 9
Dependent Claim
32 words
An SOI-type semiconductor device according to claim 3, wherein said pair of low resistivity semiconductor regions are disposed in a checker board pattern with said pair of voltage supply lines connected alternately.
Claim 10
Dependent Claim
114 words
A semiconductor-on-insulator (SOI) type semiconductor device comprising: a semiconductor substrate; an insulating layer formed on said semiconductor substrate; a plurality of active semiconductor regions disposed at a same level in said insulating layer constituting transistors of an integrated circuitry; a pair of low resistivity semiconductor regions isolated from each other and disposed at said same level in said insulating layer, said pair of low resistivity semiconductor regions and said plurality of active semiconductor regions forming a coplanar surface; a pair of voltage supply lines formed on said coplanar surface; wherein said pair of low resistivity semiconductor regions form a capacitor through capacitive coupling with said semiconductor substrate and do not constitute said integrated circuitry.
Claim 11
Dependent Claim
114 words
A semiconductor-on-insulator (SOI) type semiconductor device comprising: a semiconductor substrate; an insulating layer formed on said semiconductor substrate; a plurality of active semiconductor regions disposed at a same level in said insulating layer constituting transistors of an integrated circuitry; a pair of low resistivity semiconductor regions isolated from each other and disposed at said same level in said insulating layer, said pair of low resistivity semiconductor regions and said plurality of active semiconductor regions forming a coplanar surface; a pair of voltage supply lines formed on said coplanar surface; wherein said pair of low resistivity semiconductor regions form a capacitor through capacitive coupling with said semiconductor substrate and do not constitute said integrated circuitry.
Claim 12
Dependent Claim
18 words
An SOI-type semiconductor device according to claim 1, wherein said capacitor is disposed outside of said integrated circuitry.
Claim 13
Dependent Claim
18 words
An SOI-type semiconductor device according to claim 9, wherein said capacitor is disposed outside of said integrated circuitry.
Claim 14
Dependent Claim
25 words
An SOI-type semiconductor device according to claim 9, wherein said pair of voltage supply lines are connected to said pair of low resistivity semiconductor regions.
References Cited (Backward Citations)
US5202751A
Cited
JPS6132561A
Cited
US4989057A
Cited
US5155573A
Cited
US5378919A
Cited
US5499207A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-26 | 2002-04-27 | 2002-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-26 | 2006-04-27 | 2006-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-26 | 2010-04-27 | 2010-10-27 | $7700.00 | Window Closed / Lapsed |