US5828121A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-level conduction structure for VLSI circuits
Assignee: United Microelectronics Corp
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Filing: 1996-06-27
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Granted: 1998-10-27
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Expires: 2016-06-27
Abstract
Abstract This invention deals with the formation of the multi-level electrode metal structure and the interconnecting inter-level metal studs used in the fabrication of VLSI circuits. After the metal layers have been formed the inter-level dielectric material used in forming the structure is etched away leaving an air dielectric between the levels. The electrode metal and the inter-level metal studs are coated with a thin envelope oxide and the entire structure is covered with a passivation layer using material with a poor step coverage. The structure of this invention provides reduced parasitic capacitance, better step coverage in interconnecting layers, and improved circuit performance.
Inventors
- 👤 Water Lur
- 👤 Jiunn Yuan Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 14:12
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/42; H10W20/01; H10W20/071; H10W20/072; H10W20/43; H10W20/432; H10W20/44; H10W20/4403; H10W20/4421; H10W20/4424; H10W20/4432; H10W20/4435; H10W20/45; H10W20/46; H10W20/495; H10W20/074; H10W20/076; H10W20/077; Y; Y10; Y10S; Y10S148/00; Y10S148/073
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
126 words
A multi-level conductor structure for VLSI circuits, comprising: a silicon substrate with circuits formed therein; a base dielectric layer formed on said silicon substrate; layers of electrodes having a first layer of electrodes and higher layers of electrodes; contact studs formed in said base dielectric layer forming electrical connections between said circuits in said silicon substrate and said first layer of electrodes; a multi-level structure comprising said layers of electrodes and inter-level studs wherein said inter-level studs form electrical connections between said layers of electrodes; a thin envelope oxide coating surrounding said electrodes and said inter-level studs; and a layer of passivation material with poor step coverage entirely covering said multi-level structure including said layers of electrodes and said air dielectric between said layers of electrodes.
Claim 2
Dependent Claim
126 words
A multi-level conductor structure for VLSI circuits, comprising: a silicon substrate with circuits formed therein; a base dielectric layer formed on said silicon substrate; layers of electrodes having a first layer of electrodes and higher layers of electrodes; contact studs formed in said base dielectric layer forming electrical connections between said circuits in said silicon substrate and said first layer of electrodes; a multi-level structure comprising said layers of electrodes and inter-level studs wherein said inter-level studs form electrical connections between said layers of electrodes; a thin envelope oxide coating surrounding said electrodes and said inter-level studs; and a layer of passivation material with poor step coverage entirely covering said multi-level structure including said layers of electrodes and said air dielectric between said layers of electrodes.
Claim 3
Dependent Claim
26 words
The multi-level conductor structure of claim 1 wherein said thin envelope oxide is silicon dioxide with a thickness of between about 1000 Angstroms and 2000 Angstroms.
Claim 4
Dependent Claim
23 words
The multi-level conductor structure of claim 1 wherein said first layer of said electrodes and said higher layers of said electrodes are aluminum.
Claim 5
Dependent Claim
13 words
The multi-level conductor structure of claim 1 wherein said inter-level studs are aluminum.
Claim 6
Dependent Claim
21 words
The multi level conductor structure of claim 1 wherein said layer of passivation material with poor step coverage is silicon dioxide.
Claim 7
Dependent Claim
15 words
The multi-level conductor structure of claim 1 wherein said base dielectric layer is borophosphosilicate glass.
Claim 8
Dependent Claim
25 words
The multi-level conductor structure of claim 1 wherein said first layer of said electrodes and said higher layers of said electrodes are an aluminum alloy.
Claim 9
Dependent Claim
23 words
The multi-level conductor structure of claim 1 wherein said first layer of said electrodes and said higher layers of said electrodes are copper.
Claim 10
Dependent Claim
23 words
The multi-level conductor structure of claim 1 wherein said first layer of said electrodes and said higher layers of said electrodes are silver.
Claim 11
Dependent Claim
15 words
The multi-level conductor structure of claim 1 wherein said inter-level studs are an aluminum alloy.
Claim 12
Dependent Claim
13 words
The multi-level conductor structure of claim 1 wherein said inter-level studs are copper.
Claim 13
Dependent Claim
13 words
The multi-level conductor structure of claim 1 wherein said inter-level studs are silver.
Claim 14
Dependent Claim
20 words
The multi-level conductor structure of claim 1 wherein said layer of passivation material with poor step coverage is silicon nitride.
Claim 15
Dependent Claim
19 words
The multi-level conductor structure of claim 1 wherein said layer of passivation material with poor step coverage is polyimide.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-26 | 2002-04-27 | 2002-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-26 | 2006-04-27 | 2006-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-26 | 2010-04-27 | 2010-10-27 | $7700.00 | Window Closed / Lapsed |