US5828614A
Expired / Lapsed
US
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Memory cell sensing method and circuitry for bit line equalization
Assignee: Monterey Research LLC
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Filing: 1997-04-07
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Granted: 1998-10-27
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Expires: 2017-04-07
Abstract
Abstract A method and apparatus for sensing the state of a memory cell and equalizing bit line voltages without using ATD circuitry. One embodiment of the present invention is a memory device that includes a memory cell coupled to a pair of bit lines, a bit line load circuit coupled to the bit lines, an equalization circuit coupled to the bit lines, and a sense amplifier circuit having inputs coupled to the bit lines and an output coupled to the equalization circuit. The memory cell may be an SRAM cell with a pair of cross-coupled inverters. The equalization circuit may be an SRAM cell with a pair of inverters that are not cross coupled. The inputs of the inverters in the equalization circuit may receive signals output by the sense amplifier circuit, and the outputs of the inverters may be coupled to the pair of bit lines. The sense amplifier senses data output by the memory cell to the bit lines, and generates output signals. The equalization circuit receives the output signals and drives the bit lines with opposite data relative to the data output by the memory cell so as to equalize the bit lines.
Inventors
- 👤 Iulian Gradinariu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 02:57
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
99 words
A memory device comprising: a first bit line; a second bit line; a bit line load circuit coupled to the first and second bit lines; a memory cell couples to the first and second bit lines; a first equalization circuit having an input, a first output coupled to the first bit line, and a second output coupled to the second bit line; and a sense amplifier circuit having a first input coupled to the first bit line, a second input coupled to the second bit line, and an output coupled to the first input of the first equalization circuit.
Claim 2
Dependent Claim
99 words
A memory device comprising: a first bit line; a second bit line; a bit line load circuit coupled to the first and second bit lines; a memory cell couples to the first and second bit lines; a first equalization circuit having an input, a first output coupled to the first bit line, and a second output coupled to the second bit line; and a sense amplifier circuit having a first input coupled to the first bit line, a second input coupled to the second bit line, and an output coupled to the first input of the first equalization circuit.
Claim 3
Dependent Claim
36 words
The memory device of claim 1, wherein the first equalization circuit further includes a second input and the sense amplifier circuit further includes a second output coupled to the second input of the first equalization circuit.
Claim 4
Dependent Claim
25 words
The memory device of claim 1, further comprising: a word line coupled to the memory cell; and a select line coupled to the equalization circuit.
Claim 5
Dependent Claim
145 words
The memory device of claim 3, wherein the memory cell comprises: a first inverter having an input and an output; a second inverter having an input and an output, wherein the input of the second inverter is coupled to the output of the first inverter, and wherein the output of the second inverter is coupled to the input of the first inverter; a first access transistor having a first terminal coupled to the first bit line, a second terminal coupled to the word line, and a third terminal coupled to the input of the second inverter and the output of the first inverter; and a second access transistor having a first terminal coupled to the first bit line, a second terminal coupled to the word line, and a third terminal coupled to the input of the first inverter and the output of the second inverter.
Claim 6
Dependent Claim
145 words
The memory device of claim 3, wherein the first equalization circuit comprises: a first inverter having an input and an output, wherein the input is configured to receive a first input signal from the first output of the sense amplifier circuit; a second inverter having an input and an output, wherein the input of the second inverter is configured to receive a second input signal that corresponds to the logical complement of the first input signal; a first access transistor having a first terminal coupled to the first bit line, a second terminal coupled to the select line, and a third terminal coupled to the output of the first inverter; and a second access transistor having a first terminal coupled to the second bit line, a second terminal coupled to the select line, and a third terminal coupled to the output of the second inverter.
Claim 7
Dependent Claim
30 words
The memory device of claim 1, further comprising a reference voltage generator that supplies a reference voltage to the first and second bit lines when the memory cell is deselected.
Claim 8
Dependent Claim
92 words
The memory device of claim 6, wherein the reference voltage generator comprises: a second equalization circuit having a first input coupled to a first logic state a second input coupled to a second logic state, a first output, and a second output, wherein the first output is coupled to the second output, and a load circuit coupled between the second output of the second equalization circuit and a power source, wherein the local circuit and the second equalization circuit generate the reference voltage at the second output of the second equalization circuit.
Claim 9
Dependent Claim
15 words
The memory device of claim 1, wherein the bit line load circuit comprises a diode.
Claim 10
Dependent Claim
13 words
The memory device of claim 1, wherein the sense amplifier circuit has hysteresis.
Claim 11
Dependent Claim
91 words
A memory device comprising a first bit line; a second bit line; means, coupled to the first and second bit lines, for pulling the first and second bit lines towards a power supply voltage; means, coupled to the first and second bit lines, for storing data; means, coupled to the first and second bit lines, for sensing the data stored in the storing means; and means, coupled to the sensing means and the first and second bit lines, for generating voltages that equalize voltages on the first and second bit lines.
Claim 12
Dependent Claim
91 words
A memory device comprising a first bit line; a second bit line; means, coupled to the first and second bit lines, for pulling the first and second bit lines towards a power supply voltage; means, coupled to the first and second bit lines, for storing data; means, coupled to the first and second bit lines, for sensing the data stored in the storing means; and means, coupled to the sensing means and the first and second bit lines, for generating voltages that equalize voltages on the first and second bit lines.
Claim 13
Dependent Claim
57 words
The memory device of claim 1, wherein the memory cell outputs first data to the first and second bit lines, and the sense amplifier circuit senses the first data and causes the equalization circuit to output second data to the first and second bit lines, wherein the second data is the logical inverse of the first data.
Claim 14
Dependent Claim
116 words
A memory device comprising: a first bit line; a second bit line; a bit line load circuit coupled to the first and second bit lines; a memory cell coupled to the first and second bit lines wherein the memory cell outputs first data to the first and second bit lines; an equalization circuit coupled to the first and second bit lines; and a sense amplifier circuit coupled to the first and second bit lines and coupled in a negative feedback arrangement with the equalization circuit such that the sense amplifier causes the equalization circuit to output second data onto first and second bit lines, wherein the second data is the logical inverse of the first data.
Claim 15
Dependent Claim
116 words
A memory device comprising: a first bit line; a second bit line; a bit line load circuit coupled to the first and second bit lines; a memory cell coupled to the first and second bit lines wherein the memory cell outputs first data to the first and second bit lines; an equalization circuit coupled to the first and second bit lines; and a sense amplifier circuit coupled to the first and second bit lines and coupled in a negative feedback arrangement with the equalization circuit such that the sense amplifier causes the equalization circuit to output second data onto first and second bit lines, wherein the second data is the logical inverse of the first data.
Claim 16
Independent Claim
71 words
A method of equalizing voltages of first and second bitlines in a memory device, the method comprising the steps of: outputting first data stored in the memory cell to the first and second bitlines; sensing the first data on the bit lines; and outputting, in response to the sensing step, second data onto the first and second bit lines, wherein the second data is the logical inverse of the first data.
Claim 17
Independent Claim
71 words
A method of equalizing voltages of first and second bitlines in a memory device, the method comprising the steps of: outputting first data stored in the memory cell to the first and second bitlines; sensing the first data on the bit lines; and outputting, in response to the sensing step, second data onto the first and second bit lines, wherein the second data is the logical inverse of the first data.
Claim 18
Dependent Claim
101 words
The method of claim 13, wherein the step of outputting the first data comprises the step of outputting a first signal to the first bit line and a second signal to the second bit line, wherein the second signal is the logical inverse of the first signal, and the step of outputting the second data comprises the step of outputting a third signal to the first bit line and a fourth signal to the second bit line, wherein the third signal is the logical inverse of the first signal and the fourth signal is the logical inverse of the second signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-26 | 2002-04-27 | 2002-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-26 | 2006-04-27 | 2006-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-26 | 2010-04-27 | 2010-10-27 | $7700.00 | Window Closed / Lapsed |