Reference voltage generating circuit capable of suppressing spurious voltage

Claim 2

A reference voltage generating circuit comprising: a current mirror circuit having an input and an output; a bias current supply circuit, connected to the input of said current mirror circuit, for supplying a bias current to the input of said current mirror circuit; a switching element, connected to said bias current supply circuit, for turning ON and OFF said bias current supply circuit; an output transistor, connected to the output of said current mirror circuit, for generating a reference voltage; and a delay circuit formed by a capacitor connected to the output of said current mirror circuit.

Claim 3

A reference voltage generating circuit comprising: first and second power supply terminals; a power saving terminal; a current mirror circuit connected to said first power supply terminal and having an input and first and second outputs; a first transistor having a collector connected to said input and a base connected to said first output; a first resistor connected to an emitter of said first transistor; a second transistor having a collector connected to said first output and a base connected to said first transistor; a third transistor having a collector connected to an emitter of said second transistor and said first resistor, an emitter connected to said second power supply terminal, and a base connected to said power saving terminal; a fourth transistor having a collector connected to said second output and a base connected to the collector thereof, for generating a reference voltage; a second resistor connected between an emitter of said fourth transistor and said second power supply terminal; and a delay circuit formed by a capacitor connected to said second output.

Claim 4

A reference voltage generating circuit comprising: first and second power supply terminals; a power saving terminal; a current mirror circuit connected to said first power supply terminal and having an input and first and second outputs; a first transistor having a collector connected to said input and a base connected to said first output; a first resistor connected to an emitter of said first transistor; a second transistor having a collector connected to said first output and a base connected to said first transistor; a third transistor having a collector connected to an emitter of said second transistor and said first resistor, an emitter connected to said second power supply terminal, and a base connected to said power saving terminal; a fourth transistor having a collector connected to said second output and a base connected to the collector thereof, for generating a reference voltage; a second resistor connected between an emitter of said fourth transistor and said second power supply terminal; and a delay circuit formed by a capacitor connected to said second output.

Claim 5

The reference voltage generating circuit as set forth in claim 2, wherein said current mirror circuit comprises: a fifth transistor having an emitter connected to said first power supply terminal, a collector connected to said input and a base connected to said input; a sixth transistor having an emitter connected to said first power supply terminal, a collector connected to said first output and a base connected to said input; and a seventh transistor having an emitter connected to said first power supply terminal, a collector connected to said second output and a base connected to said input, said capacitor being connected between the collector and the base of said seventh transistor.

Claim 6

The reference voltage generating circuit as set forth in claim 3, wherein said current mirror circuit further comprises: a third resistor connected between said first power supply terminal and the emitter of said fifth transistor; a fourth resistor connected between said first power supply terminal and the emitter of said sixth transistor; and a fifth resistor connected between said first power supply terminal and the emitter of said seventh transistor.

Claim 7

A reference voltage generating circuit comprising: a power supply terminal; a ground terminal; a power saving terminal; first, second and third resistors connected to said power supply terminal; a first PNP-type transistor having an emitter connected to said first resistor, a collector and a base connected to the collector; a second PNP-type transistor having an emitter connected to said second resistor, a collector, and a base connected to the collector of said first PNP-type transistor; a third PNP-type transistor having an emitter connected to said third resistor, a collector, and a base connected to the collector of said first PNP-type transistor; a capacitor connected between the collector and the base of said third PNP-type transistor; a first NPN-type transistor having a collector connected to the collector of said first PNP-type transistor, an emitter, and a base connected to the collector of said second PNP-type transistor; a fourth resistor connected to the emitter of said first NPN-type transistor; a second NPN-type transistor having a collector connected to the collector of said second PNP-type transistor, en emitter, and a base connected to the emitter of said first PNP-type transistor; a third NPN-type transistor having a collector connected to the collector of said third PNP-type transistor, an emitter, and a base, connected to the collector of said third PNP-type transistor for generating a reference voltage; a fifth resistor connected to the emitter of said third NPN-type transistor; and a fourth NPN-type transistor having a collector connected to the emitter of said second NPN-type transistor and said fourth resistor, a base connected to said power saving terminal, and an emitter connected to said ground terminal.

Claim 8

A reference voltage generating circuit comprising: a power supply terminal; a ground terminal; a power saving terminal; first, second and third resistors connected to said power supply terminal; a first PNP-type transistor having an emitter connected to said first resistor, a collector and a base connected to the collector; a second PNP-type transistor having an emitter connected to said second resistor, a collector, and a base connected to the collector of said first PNP-type transistor; a third PNP-type transistor having an emitter connected to said third resistor, a collector, and a base connected to the collector of said first PNP-type transistor; a capacitor connected between the collector and the base of said third PNP-type transistor; a first NPN-type transistor having a collector connected to the collector of said first PNP-type transistor, an emitter, and a base connected to the collector of said second PNP-type transistor; a fourth resistor connected to the emitter of said first NPN-type transistor; a second NPN-type transistor having a collector connected to the collector of said second PNP-type transistor, en emitter, and a base connected to the emitter of said first PNP-type transistor; a third NPN-type transistor having a collector connected to the collector of said third PNP-type transistor, an emitter, and a base, connected to the collector of said third PNP-type transistor for generating a reference voltage; a fifth resistor connected to the emitter of said third NPN-type transistor; and a fourth NPN-type transistor having a collector connected to the emitter of said second NPN-type transistor and said fourth resistor, a base connected to said power saving terminal, and an emitter connected to said ground terminal.