US5838167A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and structure for loading data into several IC devices
Assignee: Xilinx Inc
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Filing: 1997-05-13
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Granted: 1998-11-17
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Expires: 2017-05-13
Abstract
Abstract An apparatus and method for decreasing the amount of time necessary to load configuration data into Field Programmable Gate Arrays (FPGAs) or other integrated circuit devices. In a preferred embodiment, serially arrayed FPGAs receive a concatenated stream of data from a common data bus. As a first FPGA reaches a loading-complete state, an enabling token is passed from the first FPGA to an enabling input on the next FPGA. The process repeats until all devices are completely loaded or fully configured.
Inventors
- 👤 Charles R. Erickson
- 👤 Lawrence Cy-Wei Hung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 12:26
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; G; G06; G06F; G06F30/00; G06F30/30; G06F30/34; H03K19/17704
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
74 words
An FPGA structure comprising: an array of FPGAs; and a common data bus having access to each such FPGA for downloading configuration data into each such FPGA without passing said configuration data through another FPGA in said array; wherein each such FPGA comprises: a first means for enabling and disabling configuration of said FPGA from said data bus; and a second means for enabling and disabling configuration of said FPGA from said data bus.
Claim 2
Dependent Claim
74 words
An FPGA structure comprising: an array of FPGAs; and a common data bus having access to each such FPGA for downloading configuration data into each such FPGA without passing said configuration data through another FPGA in said array; wherein each such FPGA comprises: a first means for enabling and disabling configuration of said FPGA from said data bus; and a second means for enabling and disabling configuration of said FPGA from said data bus.
Claim 3
Dependent Claim
127 words
The FGPA structure of claim 1, wherein: each such FPGA has an output enable signal, a first input enable signal, and a second input enable signal; said first means for enabling and disabling configuration of said FPGA comprises a common enable signal driving said first input enable signal of each FPGA in said array of FPGAs; said second means for enabling and disabling configuration of said FPGA comprises said second input enable signal; in a first such FPGA said second input enable signal is driven by a load signal; and in all other such FPGAs in said array of FPGAs, said second input enable signal is driven by said output enable signal of another such FPGA, thereby forming a daisy chain of enable signals for said FPGAs.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-16 | 2002-05-18 | 2002-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-16 | 2006-05-18 | 2006-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-16 | 2010-05-18 | 2010-11-17 | $7700.00 | Window Closed / Lapsed |