ATM communication system interconnect/termination unit

Claim 2

A data-structure driven asynchronous transfer mode (ATM) communication device for receiving, processing, and transmitting a plurality of data cells in an ATM communication system network, said device comprising: memory means for receiving, storing and recovering data cells, and data-structures of linked lists with memory address pointers to starting and ending memory addresses as well as internal memory address pointers to successive elements of said linked-list data structures by memory addresses in succession and regression; a permanently pre-configured processor configured to segment ATM data cells for storage in said memory means, and to reassemble said segmented ATM data cells stored in said memory means, and using said memory address pointers to recover and reassemble said data cells; input/output (I/O) port interface means for communicating said device with an ATM communication system network; a programmable processor exercising executive control over said pre-configured processor and said input/output port interface means, said programmable processor creating in said memory means a descriptor for each of said data-structures of linked lists; a timer unit including plural hardware-implemented timers; and a scheduler unit including means for maintaining a calendar based schedule table with pointers to memory locations of virtual connections of said ATM communication system network to be serviced by said pre-configured processor in a particular ATM cell time slot; wherein said programmable processor also includes means for exercising executive control over said timer unit and said scheduler unit.

Claim 3

The ATM communication device of claim 1 wherein said programmable processor includes means for creating a descriptor in said memory means both for each received data cell, and for each data cell to be transmitted over said ATM communication system network.

Claim 4

The ATM communication device of claim 1 wherein said device includes a singular semiconductor substrate upon which is formed said memory means, said permanently pre-configured processor, said timer unit, said scheduler unit, said programmable processor, and said I/O port interface means.

Claim 5

The ATM communication device of claim 1 wherein said device further includes as part of said I/O port interface means a permanently pre-configured second processor configured to manage a Free-Cell-List portion and a Transmit-and-Receive first-in-first-out (FIFO) portion of said memory means.

Claim 6

The ATM communication device of claim 1 wherein said device further includes as part of said I/O port interface means a permanently pre-configured second processor configured to manage a Free-Cell-List portion and a Transmit-and-Receive first-in-first-out (FIFO) portion of said memory means.

Claim 7

The ATM communication device of claim 1 wherein said means for maintaining a calendar based schedule table includes a permanently pre-configured third processor configured to maintain said calendar-based schedule table.

Claim 8

The ATM communication device of claim 1 wherein said device further includes a primary port interface means, and a secondary port interface means.

Claim 9

The ATM communication device of claim 1 wherein said device further includes a processor memory accessible to said programmable processor.

Claim 10

The ATM communication device of claim 2 wherein said device includes a processor memory carried on said singular semiconductor substrate and accessible to said programmable processor.

Claim 11

A data-structure driven asynchronous transfer mode (ATM) communication device for receiving, processing, and transmitting a plurality of data cells in an ATM communication system network, said device comprising: memory means for receiving, storing and recovering data cells, and data-structures of linked lists with memory as internal memory address pointers to successive elements of said linked-list data structures by memory addresses in succession and regression; a permanently pre-configured first processor configured to segment ATM data cells for storage in said memory means, and to reassemble said segmented ATM data cells stored in said memory means, and using said memory address pointers to recover and reassemble said data cells; input/output (I/O) port interface means for communicating said device with the ATM communication system network; a permanently pre-configured second processor portion of said I/O port interface means configured to manage a Free-Cell-List portion and a Transmit-and-Receive first-in-first-out (FIFO) portion of said memory means; a primary port interface means; a secondary port interface means; a timer unit including plural hardware-implemented timers; a scheduler unit including means for maintaining a calendar based schedule table with pointers to memory locations of virtual connections of said ATM communication system network to be serviced by said pre-configured second processor in a particular ATM data cell time slot; a permanently pre-configured third processor configured to maintain said calendar-based schedule table; a programmable processor exercising executive control over said pre-configured processor and said input/output port interface means, over said timer unit and said scheduler unit, said programmable processor creating in said memory means a descriptor for each of said data-structures of linked lists; and a processor memory accessible to said programmable processor.

Claim 12

A data-structure driven asynchronous transfer mode (ATM) communication device for receiving, processing, and transmitting a plurality of data cells in an ATM communication system network, said device comprising: memory means for receiving, storing and recovering data cells, and data-structures of linked lists with memory as internal memory address pointers to successive elements of said linked-list data structures by memory addresses in succession and regression; a permanently pre-configured first processor configured to segment ATM data cells for storage in said memory means, and to reassemble said segmented ATM data cells stored in said memory means, and using said memory address pointers to recover and reassemble said data cells; input/output (I/O) port interface means for communicating said device with the ATM communication system network; a permanently pre-configured second processor portion of said I/O port interface means configured to manage a Free-Cell-List portion and a Transmit-and-Receive first-in-first-out (FIFO) portion of said memory means; a primary port interface means; a secondary port interface means; a timer unit including plural hardware-implemented timers; a scheduler unit including means for maintaining a calendar based schedule table with pointers to memory locations of virtual connections of said ATM communication system network to be serviced by said pre-configured second processor in a particular ATM data cell time slot; a permanently pre-configured third processor configured to maintain said calendar-based schedule table; a programmable processor exercising executive control over said pre-configured processor and said input/output port interface means, over said timer unit and said scheduler unit, said programmable processor creating in said memory means a descriptor for each of said data-structures of linked lists; and a processor memory accessible to said programmable processor.

Claim 13

The ATM communication device of claim 10 wherein said programmable processor includes means for creating a descriptor in said memory means both for each received data cell, and for each data cell to be transmitted over said ATM communication system network.

Claim 14

The ATM communication device of claim 10 wherein said device includes a singular semiconductor substrate upon which is formed said memory means, said permanently pre-configured first processor; said permanently pre-configured second processor portion; said permanently pre-configured third processor; said primary port interface means; said secondary port interface means; said input/output (I/O) port interface means; said timer unit; said scheduler unit; said programmable processor; and said processor memory.

Claim 15

The ATM communication device of claim 10 wherein said programmable processor device includes an arithmetic logic unit, a load/store/add unit, a branch command unit, a multiply/shift command unit, a coprocessor interface unit, and a bus interface unit.

Claim 16

A data-structure driven method for receiving, processing, and transmitting a plurality of data cells in an asynchronous transfer mode (ATM) communication system network, said method comprising: providing memory means for receiving, storing and recovering data cells; creating in said memory means data-structures of linked lists with memory address pointers to starting and ending memory addresses as well as internal memory address pointers to successive elements of said linked-list data structures by memory addresses in succession and regression; providing a permanently pre-configured processor, and configuring said pre-configured processor to segment ATM data cells for storage in said memory means, and to reassemble said segmented ATM data cells stored in said memory means, using said memory address pointers to recover and reassemble said data cells; providing an input/output (I/O) port interface means for communicating with the ATM communication system network; providing a programmable processor, and utilizing said programmable processor to exercise executive control over said pre-configured processor and said input/output port interface means, as well as using said programmable processor to create in said memory means a descriptor for each of said data-structures of linked lists; providing a timer unit with plural hardware-implemented timers; providing a scheduler unit including means for maintaining a calendar-based schedule table with pointers to memory locations of virtual connections of said ATM communication system network to be serviced by said pre-configured processor in a particular ATM data cell time slot; and providing for said programmable processor to also exercise executive control over said timer unit and said scheduler unit.

Claim 17

A data-structure driven method for receiving, processing, and transmitting a plurality of data cells in an asynchronous transfer mode (ATM) communication system network, said method comprising: providing memory means for receiving, storing and recovering data cells; creating in said memory means data-structures of linked lists with memory address pointers to starting and ending memory addresses as well as internal memory address pointers to successive elements of said linked-list data structures by memory addresses in succession and regression; providing a permanently pre-configured processor, and configuring said pre-configured processor to segment ATM data cells for storage in said memory means, and to reassemble said segmented ATM data cells stored in said memory means, using said memory address pointers to recover and reassemble said data cells; providing an input/output (I/O) port interface means for communicating with the ATM communication system network; providing a programmable processor, and utilizing said programmable processor to exercise executive control over said pre-configured processor and said input/output port interface means, as well as using said programmable processor to create in said memory means a descriptor for each of said data-structures of linked lists; providing a timer unit with plural hardware-implemented timers; providing a scheduler unit including means for maintaining a calendar-based schedule table with pointers to memory locations of virtual connections of said ATM communication system network to be serviced by said pre-configured processor in a particular ATM data cell time slot; and providing for said programmable processor to also exercise executive control over said timer unit and said scheduler unit.

Claim 18

The method of claim 14 further including the step of using said programmable processor to create a descriptor in said memory means both for each received data cell, and for each data cell to be transmitted over said ATM communication system network.

Claim 19

The method of claim 14 including the steps of providing a singular semiconductor substrate; and forming upon said singular semiconductor substrate said memory means, said permanently pre-configured processor, said timer unit, said scheduler unit, said programmable processor, and said I/O port interface means.

Claim 20

The method of claim 14 further including the step of includes as part of said I/O port interface means a permanently pre-configured second processor configured to manage a Free-Cell-List portion and a Transmit-and-Receive first-in-first-out (FIFO) portion of said memory means.

Claim 21

The method of claim 14 further including the step of providing a permanently pre-configured third processor configured to maintain said calendar-based schedule table.

Claim 22

The method of claim 14 further including the steps of providing a primary port interface means, and a secondary port interface means.

Claim 23

The method of claim 14 further including the steps of providing a processor memory accessible to said programmable processor, and forming this processor memory on a single substrate with said programmable processor.