US5844424A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmably bidirectional buffered interconnect circuit
Assignee: Xilinx Inc
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Filing: 1997-02-28
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Granted: 1998-12-01
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Expires: 2017-02-28
Abstract
Abstract A programmable bidirectional interconnect circuit selectively provides either a buffered connection, a non-buffered connection, or a disconnection (tristate mode). The circuit includes six transistors coupled to a buffer and two signal lines.
Inventors
- 👤 Sridhar Krishnamurthy
- 👤 Shekhar Bapat
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:31
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018585; H03K19/018592
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
117 words
A programmable bidirectional interconnect circuit comprising: a buffer having an input terminal and an output terminal; first and second signal lines; a first transistor connected between said first signal line and said input terminal of said buffer; a transistor pair, including second and third transistors, connected between said second signal line and said input terminal of said buffer; a fourth transistor connected to said first signal line; a fifth transistor connected to said second signal line; a sixth transistor connected to said output terminal of said buffer, said fourth transistor, and said fifth transistor; first control means for controlling said first, second, fourth, and fifth transistors; and second control means for controlling said third and sixth transistors.
Claim 2
Dependent Claim
117 words
A programmable bidirectional interconnect circuit comprising: a buffer having an input terminal and an output terminal; first and second signal lines; a first transistor connected between said first signal line and said input terminal of said buffer; a transistor pair, including second and third transistors, connected between said second signal line and said input terminal of said buffer; a fourth transistor connected to said first signal line; a fifth transistor connected to said second signal line; a sixth transistor connected to said output terminal of said buffer, said fourth transistor, and said fifth transistor; first control means for controlling said first, second, fourth, and fifth transistors; and second control means for controlling said third and sixth transistors.
Claim 3
Dependent Claim
117 words
A programmable bidirectional interconnect circuit comprising: a buffer having an input terminal and an output terminal; first and second signal lines; a first transistor connected between said first signal line and said input terminal of said buffer; a transistor pair, including second and third transistors, connected to said second signal line; a fourth transistor connected to said first signal line; a fifth transistor connected between said second signal line and said input terminal of said buffer; a sixth transistor connected to said output terminal of said buffer, said transistor pair, and said fourth transistor; first control means for controlling said first, second, fourth, and fifth transistors; and second control means for controlling said third and sixth transistors.
Claim 4
Dependent Claim
117 words
A programmable bidirectional interconnect circuit comprising: a buffer having an input terminal and an output terminal; first and second signal lines; a first transistor connected between said first signal line and said input terminal of said buffer; a transistor pair, including second and third transistors, connected to said second signal line; a fourth transistor connected to said first signal line; a fifth transistor connected between said second signal line and said input terminal of said buffer; a sixth transistor connected to said output terminal of said buffer, said transistor pair, and said fourth transistor; first control means for controlling said first, second, fourth, and fifth transistors; and second control means for controlling said third and sixth transistors.
References Cited (Backward Citations)
US4855619A
Cited
US5517135A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-30 | 2002-06-01 | 2002-12-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-30 | 2006-06-01 | 2006-12-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-30 | 2010-06-01 | 2010-12-01 | $7700.00 | Window Closed / Lapsed |