US5847441A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor junction antifuse circuit
Assignee: Micron Technology Inc
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Filing: 1996-05-10
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Granted: 1998-12-08
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Expires: 2016-05-10
Abstract
Abstract An integrated semiconductor junction antifuse is formed from either adjacent regions of opposite doping types or spaced apart regions of similar doping type within a substrate. In its unblown state, the junction antifuse forms an open circuit that blocks current from flowing while in the blown state, the junction antifuse conducts current. The junction antifuse is blown by applying a breakdown voltage sufficient to overcome a semiconductor junction so that current flows across the reverse-biased semiconductor junction. As current flows across the reverse-biased junction, dopant migration forms a conductive path so that the junction antifuse no longer forms an open circuit.
Inventors
- 👤 Douglas J. Cutter
- 👤 Kurt D. Beigel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:05
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/16; G11C17/18; H; H10; H10B; H10B20/00; H10B20/20; H10B20/25
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
131 words
An integrated circuit assembly including: an integrated device having a plurality of operational modes, the integrated device being responsive to a control signal to select one of the operating modes; an input node; and a programmable integrated sensing circuit having a semiconductor junction having a first region coupled to the input node, the semiconductor junction in an unblown state blocking current flow and in a blown state conducting current, the sensing circuit being configured to set the control signal to a first state in response to the semiconductor junction being programmed to the blown state and to set the control signal to a second state in response to the semiconductor function being programmed to the unblown state, the sensing circuit being coupled to provide the control signal to the integrated device.
Claim 2
Dependent Claim
131 words
An integrated circuit assembly including: an integrated device having a plurality of operational modes, the integrated device being responsive to a control signal to select one of the operating modes; an input node; and a programmable integrated sensing circuit having a semiconductor junction having a first region coupled to the input node, the semiconductor junction in an unblown state blocking current flow and in a blown state conducting current, the sensing circuit being configured to set the control signal to a first state in response to the semiconductor junction being programmed to the blown state and to set the control signal to a second state in response to the semiconductor function being programmed to the unblown state, the sensing circuit being coupled to provide the control signal to the integrated device.
Claim 3
Dependent Claim
28 words
The integrated circuit of claim 1, further including: a precharge circuit coupled to the input node; and a buffer circuit having an input coupled to the input node.
Claim 4
Dependent Claim
68 words
The sensing circuit of claim 1, further including a sense switch serially coupled with the semiconductor junction between the input node and a reference node, the sense switch having a control input, the sense switch passing current in response to a signal of a first state at the control input, the sense switch blocking current in response to a signal of a second state at the control input.
Claim 5
Dependent Claim
23 words
The integrated circuit of claim 3 wherein the sense switch is a transistor and the control input is the gate of the transistor.
Claim 6
Dependent Claim
123 words
A computer system, comprising: an input device; an output device; a data storage device; computer circuitry coupled to the input device, the output device and the data storage device, the computer circuitry including an integrated circuit package, the integrated circuit package including: an integrated device having a mode control input, the integrated device operating in a first operational mode in response to a first voltage at the mode select input and operating in a second operational mode in response to a second voltage at the mode select input; a biasing voltage terminal; and a semiconductor junction antifuse coupled between the biasing voltage and the mode select input, the conductive state of the semiconductor junction antifuse controlling the voltage at the mode select input.
Claim 7
Dependent Claim
123 words
A computer system, comprising: an input device; an output device; a data storage device; computer circuitry coupled to the input device, the output device and the data storage device, the computer circuitry including an integrated circuit package, the integrated circuit package including: an integrated device having a mode control input, the integrated device operating in a first operational mode in response to a first voltage at the mode select input and operating in a second operational mode in response to a second voltage at the mode select input; a biasing voltage terminal; and a semiconductor junction antifuse coupled between the biasing voltage and the mode select input, the conductive state of the semiconductor junction antifuse controlling the voltage at the mode select input.
Claim 8
Dependent Claim
75 words
The computer system of claim 5 wherein the junction antifuse includes: a substrate of a first doping type; a first region of the first doping type in the substrate; and a second region of a second doping type different from the first type in the substrate and adjacent the first region, the doping levels of the first and second regions being selected to form a junction having a breakdown voltage below the minimum breakdown voltage.
Claim 9
Dependent Claim
31 words
The computer system of claim 6 wherein the doping levels of the first region is higher than substantially all other doping levels of the first doping type in the integrated device.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-07 | 2002-06-08 | 2002-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-07 | 2006-06-08 | 2006-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-07 | 2010-06-08 | 2010-12-08 | $7700.00 | Window Closed / Lapsed |