US5847577A
Expired / Lapsed
US
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DRAM memory cell for programmable logic devices
Assignee: Xilinx Inc
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Filing: 1996-11-01
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Granted: 1998-12-08
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Expires: 2016-11-01
Abstract
Abstract A plurality of DRAM cells are used to store the state of the programmable points in a programmable logical device (e.g., a field programmable gate array or FPGA). An individual DRAM cell is used in conjunction with each programmable interconnect point (PIP) within the FPGA to hold a logical state indicating the connectivity state of the PIP. During a refresh cycle, each DRAM memory cell is loaded with its current logical state in order to maintain this state within the PIP. An information store contains duplicate data for each DRAM cell and this duplicate data is supplied and read during the refresh cycle in order to provide each DRAM cell with its proper logical state. In this manner, the refresh cycle does not alter the logic configuration of its associated FPGA DRAM cell. The information store can be a plurality of DRAM cells or the information store can be of non-volatile memory, for instance, read only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), or of non-volatile magnetic storage.
Inventors
- 👤 Stephen M. Trimberger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 14:10
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/693; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17748; H03K19/1776; H03K19/17764; H03K19/17772
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
102 words
A circuit for implementing a programmable interconnect point in a programmable logic device, said circuit comprising: a switch; a DRAM memory cell associated with said switch, said DRAM memory cell adapted to set and store the state of said switch; a receiving circuit for receiving a duplicate value indicative of said state of said switch; circuitry for receiving a data valid signal indicating a valid interval in which said duplicate value is to be stored into said DRAM memory cell; and circuitry responsive to said valid signal for storing said duplicate value into said DRAM memory cell during a memory refresh cycle.
Claim 2
Dependent Claim
102 words
A circuit for implementing a programmable interconnect point in a programmable logic device, said circuit comprising: a switch; a DRAM memory cell associated with said switch, said DRAM memory cell adapted to set and store the state of said switch; a receiving circuit for receiving a duplicate value indicative of said state of said switch; circuitry for receiving a data valid signal indicating a valid interval in which said duplicate value is to be stored into said DRAM memory cell; and circuitry responsive to said valid signal for storing said duplicate value into said DRAM memory cell during a memory refresh cycle.
Claim 3
Dependent Claim
58 words
The circuit of claim 1 further comprising a shadow memory array comprising a plurality of memory cells, each memory cell associated with a switch of said programmable logic device and adapted to store said state of said switch in parallel with said DRAM memory cell and also adapted to supply said duplicate value during said memory refresh cycle.
Claim 4
Dependent Claim
89 words
The circuit of claim 1 wherein said circuit further comprises: a data line for providing a data signal to said programmable interconnect point; an address line for providing an address signal to said programmable interconnect point; a pass transistor coupled to said data and address lines and adapted to transfer said data signal to said DRAM memory cell if said address signal is provided to said first pass transistor, wherein said switch is operable in response to the state of the data signal stored by said DRAM memory cell.
Claim 5
Dependent Claim
20 words
The circuit of claim 2 wherein said plurality of memory cells of said shadow memory array are non-volatile memory cells.
Claim 6
Dependent Claim
23 words
The circuit of claim 1 wherein said circuit further comprises a data register for storing said duplicate value during said memory refresh cycle.
Claim 7
Dependent Claim
35 words
The circuit of claim 2 wherein said circuit further comprises an address sequencer for continuously addressing said plurality of memory cells of said shadow memory array and corresponding DRAM memory cells during a refresh sequence.
Claim 8
Dependent Claim
39 words
The circuit of claim 1 wherein said circuit further comprises a circuit for generating said valid signal during said memory refresh cycle such that said valid signal is asserted when valid data is present at said DRAM memory cell.
Claim 9
Dependent Claim
28 words
The circuit of claim 6 wherein said circuit further comprises a circuit for detecting and correcting errors in said plurality of memory cells of said shadow memory array.
Claim 10
Dependent Claim
139 words
A circuit for implementing a programmable interconnect point in a programmable logic device, said circuit comprising: a switch; a DRAM memory cell associated with said switch, said DRAM memory cell adapted to set and store the state of said switch; circuitry for receiving a data valid signal indicating a valid interval in which a duplicate value is to be stored into said DRAM memory cell; circuitry responsive to said data valid signal for storing said duplicate value into said switch during a memory refresh cycle; and a shadow memory array comprising a plurality of non-volatile memory cells, each non-volatile memory cell associated with a respective switch of said programmable logic device and adapted to store said state of said switch in parallel with said DRAM memory cell and adapted to supply said duplicate value during said memory refresh cycle.
Claim 11
Dependent Claim
139 words
A circuit for implementing a programmable interconnect point in a programmable logic device, said circuit comprising: a switch; a DRAM memory cell associated with said switch, said DRAM memory cell adapted to set and store the state of said switch; circuitry for receiving a data valid signal indicating a valid interval in which a duplicate value is to be stored into said DRAM memory cell; circuitry responsive to said data valid signal for storing said duplicate value into said switch during a memory refresh cycle; and a shadow memory array comprising a plurality of non-volatile memory cells, each non-volatile memory cell associated with a respective switch of said programmable logic device and adapted to store said state of said switch in parallel with said DRAM memory cell and adapted to supply said duplicate value during said memory refresh cycle.
Claim 12
Dependent Claim
89 words
The circuit of claim 9 wherein said circuit further comprises: a data line for providing a data signal to said programmable interconnect point; an address line for providing an address signal to said programmable interconnect point; a pass transistor coupled to said data and address lines and adapted to transfer said data signal to said DRAM memory cell if said address signal is provided to said first pass transistor, wherein said switch is operable in response to the state of the data signal stored by said DRAM memory cell.
Claim 13
Dependent Claim
23 words
The circuit of claim 9 wherein said circuit further comprises a data register for storing said duplicate value during said memory refresh cycle.
Claim 14
Dependent Claim
36 words
The circuit of claim 9 wherein said circuit further comprises an address sequencer for continuously addressing said plurality of non-volatile memory cells of said shadow memory array and corresponding DRAM memory cells during a refresh sequence.
Claim 15
Dependent Claim
39 words
The circuit of claim 9 wherein said circuit further comprises a circuit for generating said valid signal during said memory refresh cycle such that said valid signal is asserted when valid data is present at said DRAM memory cell.
Claim 16
Dependent Claim
29 words
The circuit of claim 13 wherein said circuit further comprises a circuit for detecting and correcting errors in said plurality of non-volatile memory cells of said shadow memory array.
Claim 17
Independent Claim
110 words
A method for maintaining a state of a switch of a programmable interconnect point in a programmable logic device, said method comprising the steps of: controlling said switch with a DRAM memory cell associated with said switch, said DRAM memory cell adapted to set and store the state of said switch; receiving from a memory array a duplicate value indicative of said state of said switch; generating a data valid signal indicating a valid interval in which said duplicate value is to be stored into said DRAM memory cell; and responsive to said data valid signal, storing said duplicate value into said DRAM memory cell during a memory refresh cycle.
Claim 18
Independent Claim
110 words
A method for maintaining a state of a switch of a programmable interconnect point in a programmable logic device, said method comprising the steps of: controlling said switch with a DRAM memory cell associated with said switch, said DRAM memory cell adapted to set and store the state of said switch; receiving from a memory array a duplicate value indicative of said state of said switch; generating a data valid signal indicating a valid interval in which said duplicate value is to be stored into said DRAM memory cell; and responsive to said data valid signal, storing said duplicate value into said DRAM memory cell during a memory refresh cycle.
Claim 19
Dependent Claim
87 words
The method of claim 15 further comprising the step of: providing a data signal over a data line to said programmable interconnect point; providing an address signal over an address line to said programmable interconnect point; and transferring said data signal to said DRAM memory cell over a pass transistor coupled to said data and address lines provided said address signal is provided to said pass transistor, wherein said switch is operable in response to the state of the data signal stored by said DRAM memory cell.
Claim 20
Dependent Claim
24 words
The method of claim 15 further comprising the step of storing said duplicate value during said memory refresh cycle in a data register circuit.
Claim 21
Dependent Claim
32 words
The method of claim 15 further comprising the step of continuously addressing said memory array and corresponding DRAM memory cells of programmable interconnect points during a refresh sequence via an address sequencer.
Claim 22
Dependent Claim
36 words
The method of claim 15 further comprising the step of generating said valid signal during said memory refresh cycle such that said valid signal is asserted when valid data is present at said DRAM memory cell.
Claim 23
Dependent Claim
21 words
The method of claim 19 further comprising the step of detecting and correcting errors in data supplied by said memory array.
Claim 24
Dependent Claim
13 words
The method of claim 15 wherein said memory array comprises non-volatile memory cells.
Claim 25
Dependent Claim
98 words
A circuit for implementing a programmable interconnect point in a programmable logic device, said circuit comprising: a switch; a memory cell associated with said switch, said memory cell adapted to set and store the state of said switch; a receiving circuit for receiving a duplicate value indicative of said state of said switch; circuitry for receiving a data valid signal indicating a valid interval in which said duplicate value is to be stored into said memory cell; and circuitry responsive to said valid signal for storing said duplicate value into said memory cell during a memory refresh cycle.
Claim 26
Dependent Claim
98 words
A circuit for implementing a programmable interconnect point in a programmable logic device, said circuit comprising: a switch; a memory cell associated with said switch, said memory cell adapted to set and store the state of said switch; a receiving circuit for receiving a duplicate value indicative of said state of said switch; circuitry for receiving a data valid signal indicating a valid interval in which said duplicate value is to be stored into said memory cell; and circuitry responsive to said valid signal for storing said duplicate value into said memory cell during a memory refresh cycle.
Claim 27
Dependent Claim
57 words
The circuit of claim 22 further comprising a shadow memory array comprising a plurality of memory cells, each memory cell associated with a switch of said programmable logic device and adapted to store said state of said switch in parallel with said memory cell and also adapted to supply said duplicate value during said memory refresh cycle.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-07 | 2002-06-08 | 2002-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-07 | 2006-06-08 | 2006-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-07 | 2010-06-08 | 2010-12-08 | $7700.00 | Window Closed / Lapsed |