US5856926A — Logic synthesis method and system with intermedia…

Claim 1

Independent Claim 343 words

An incremental logic synthesis system for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction, comprising: an old logic file; an old circuit file for storing an old circuit generated from said old logic file and optimized to satisfy the design constriction; logic capture means for inputting a new logic file partially chanced from said old logic file; logic synthesizing means for generating a first intermediate circuit file for storing a first intermediate circuit from said new logic file; circuit updating means for discriminating a common sub-circuit of said old circuit having an equivalent logic function and an uncommon sub-circuit of said first intermediate circuit having an inconsistent logic function from said old circuit file and said first intermediate circuit file; and circuit optimizing means for generating a second intermediate circuit file for storing a second intermediate circuit, by merging the common sub-circuit of said old circuit and the uncommon sub-circuit of said first intermediate circuit and optimizing said uncommon sub-circuit of said second intermediate circuit so as to satisfy the design constriction, wherein said circuit updating means comprises: corresponding flip-flop pair discriminating means for discriminating a pair of flip-flops in said old circuit in said old circuit file and a flip-flop in said first intermediate circuit in said first intermediate circuit file, by using as a search key a name of a primary input/output signal to and from the circuit, and cone function comparing means for comparing the function of a cone having a gate combinational circuit with one output in said old circuit with the function of a cone having a gate combinational circuit with one output in said first intermediate circuit, selecting a circuit containing at least one gate in a cone of said old circuit with an equivalent logic function, as said common sub-circuit, and selecting a circuit containing a gate in a cone of said first intermediate circuit with an inconsistent logic function and a circuit containing a gate in a cone not identified as the comparison object, as said uncommon sub-circuit.

Claim 2

Dependent Claim 343 words

An incremental logic synthesis system for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction, comprising: an old logic file; an old circuit file for storing an old circuit generated from said old logic file and optimized to satisfy the design constriction; logic capture means for inputting a new logic file partially chanced from said old logic file; logic synthesizing means for generating a first intermediate circuit file for storing a first intermediate circuit from said new logic file; circuit updating means for discriminating a common sub-circuit of said old circuit having an equivalent logic function and an uncommon sub-circuit of said first intermediate circuit having an inconsistent logic function from said old circuit file and said first intermediate circuit file; and circuit optimizing means for generating a second intermediate circuit file for storing a second intermediate circuit, by merging the common sub-circuit of said old circuit and the uncommon sub-circuit of said first intermediate circuit and optimizing said uncommon sub-circuit of said second intermediate circuit so as to satisfy the design constriction, wherein said circuit updating means comprises: corresponding flip-flop pair discriminating means for discriminating a pair of flip-flops in said old circuit in said old circuit file and a flip-flop in said first intermediate circuit in said first intermediate circuit file, by using as a search key a name of a primary input/output signal to and from the circuit, and cone function comparing means for comparing the function of a cone having a gate combinational circuit with one output in said old circuit with the function of a cone having a gate combinational circuit with one output in said first intermediate circuit, selecting a circuit containing at least one gate in a cone of said old circuit with an equivalent logic function, as said common sub-circuit, and selecting a circuit containing a gate in a cone of said first intermediate circuit with an inconsistent logic function and a circuit containing a gate in a cone not identified as the comparison object, as said uncommon sub-circuit.

Claim 3

Dependent Claim 52 words

An incremental logic synthesis system according to claim 1, wherein said logic synthesizing means converts a Boolean algebra expression in a logic file into a corresponding gate circuit expression, a corresponding flip-flop circuit expression, and an interconnection circuit expression for interconnecting the corresponding gate circuit expression and the corresponding flip-flop circuit expression.

Claim 4

Dependent Claim 60 words

An incremental logic synthesis system according to claim 1, wherein said optimizing means includes judgement means for judging whether at least one of the conditions selected from a group consisting of the number of gates in the circuit, a power consumption of the circuit, and a layout of the circuit is satisfied or not, and for displaying the judgement result.

Claim 5

Dependent Claim 70 words

An incremental logic synthesis system according to claim 1, wherein said corresponding flip-flop pair discriminating means selects a pair of flip-flops in the order of larger common primary input signal ratio if the number of primary input signals to said first intermediate circuit is larger than the number of primary output signals from said first intermediate circuit, and if smaller, in the order of larger common primary output signal ratio.

Claim 6

Dependent Claim 59 words

An incremental logic synthesis system according to claim 4, wherein if a corresponding flip-flop pair cannot be identified by using said common primary input or output signal ratio, a pair of flip-flops is selected from an unidentified flip-flop pair group, by using at least one of indices including a common input flip-flop ratio and a common output flip-flop ratio.

Claim 7

Dependent Claim 119 words

An incremental logic synthesis system according to claim 1, wherein said cone function comparing means further judges whether one of a pair of cones with inconsistent logic functions has an inversion function of the other, if an inversion function, a new cone with an inversion function is formed either by deleting an inverter in the cone of said old circuit at the most output side, or inserting an inverter in the cone at the most output side, or switching a signal to an inverting output terminal of a gate of the cone at the most output side, and all gates contained in said new cone with an inversion function are added to the common sub-circuit of said old circuit.

Claim 8

Dependent Claim 332 words

An incremental logic synthesis method for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction, comprising the steps of: inputting an old logic file, an old circuit file for storing an old circuit generated from said old logic file and optimized to satisfy the design constriction, and a new logic file partially changed from said old logic file; generating a first intermediate circuit file for storing a first intermediate circuit from said new logic file; updating by discriminating a common sub-circuit of said old circuit having an equivalent logic function and an uncommon sub-circuit of said first intermediate circuit having an inconsistent logic function from said old circuit file and said first intermediate circuit; and optimizing by generating a second intermediate circuit file for storing a second intermediate circuit, by merging the common sub-circuit of said old circuit and the uncommon sub-circuit of said first intermediate circuit, and optimizing said uncommon sub-circuit of said second intermediate circuit so as to satisfy the design constriction, wherein said updating step comprises the steps of: discriminating a corresponding flip-flop pair by discriminating a pair of flip flops in said old circuit in said old circuit file and a flip-flop in said first intermediate circuit in said first intermediate circuit file, by using as a search key a name of a primary input/output signal to and from the circuit, and comparing the function of a cone having a gate combinational circuit with one output in said old circuit with the function of a cone having a gate combinational circuit with one output in said first intermediate circuit, selecting a circuit containing at least one gate in a cone of said old circuit with an equivalent logic function, as said common sub-circuit, and selecting a circuit containing a gate in a cone of said first intermediate circuit with an inconsistent logic function and a circuit containing a gate in a cone not identified as the comparison object, as said uncommon sub-circuit.

Claim 9

Dependent Claim 332 words

An incremental logic synthesis method for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction, comprising the steps of: inputting an old logic file, an old circuit file for storing an old circuit generated from said old logic file and optimized to satisfy the design constriction, and a new logic file partially changed from said old logic file; generating a first intermediate circuit file for storing a first intermediate circuit from said new logic file; updating by discriminating a common sub-circuit of said old circuit having an equivalent logic function and an uncommon sub-circuit of said first intermediate circuit having an inconsistent logic function from said old circuit file and said first intermediate circuit; and optimizing by generating a second intermediate circuit file for storing a second intermediate circuit, by merging the common sub-circuit of said old circuit and the uncommon sub-circuit of said first intermediate circuit, and optimizing said uncommon sub-circuit of said second intermediate circuit so as to satisfy the design constriction, wherein said updating step comprises the steps of: discriminating a corresponding flip-flop pair by discriminating a pair of flip flops in said old circuit in said old circuit file and a flip-flop in said first intermediate circuit in said first intermediate circuit file, by using as a search key a name of a primary input/output signal to and from the circuit, and comparing the function of a cone having a gate combinational circuit with one output in said old circuit with the function of a cone having a gate combinational circuit with one output in said first intermediate circuit, selecting a circuit containing at least one gate in a cone of said old circuit with an equivalent logic function, as said common sub-circuit, and selecting a circuit containing a gate in a cone of said first intermediate circuit with an inconsistent logic function and a circuit containing a gate in a cone not identified as the comparison object, as said uncommon sub-circuit.

Claim 10

Dependent Claim 51 words

An incremental logic synthesis method according to claim 7, wherein said generating step converts a Boolean algebra expression in a logic file into a corresponding gate circuit expression, a corresponding flip-flop circuit expression, and an interconnection circuit expression for interconnecting the corresponding gate circuit expression and the corresponding flip-flop circuit expression.

Claim 11

Dependent Claim 61 words

An incremental logic synthesis method according to claim 7, wherein said optimizing step includes a judgement step of judging whether at least one of the conditions selected from a group consisting of the number of gates in the circuit, a power consumption of the circuit, and a layout of the circuit is satisfied or not, and for displaying the judgement result.

Claim 12

Dependent Claim 70 words

An incremental logic synthesis method according to claim 7, wherein said corresponding flip-flop pair discriminating step selects a pair of flip-flops in the order of larger common primary input signal ratio if the number of primary input signals to said first intermediate circuit is larger than the number of primary output signals from said first intermediate circuit, and if smaller, in the order of larger common primary output signal ratio.

Claim 13

Dependent Claim 59 words

An incremental logic synthesis method according to claim 10, wherein if a corresponding flip-flop pair cannot be identified by using said common primary input or output signal ratio, a pair of flip-flops is selected from an unidentified flip-flop pair group, by using at least one of indices including a common input flip-flop ratio and a common output flip-flop ratio.

Claim 14

Dependent Claim 286 words

An incremental logic synthesis system for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction, comprising: an old logic file; an old circuit file for storing an old circuit generated from said old logic file and optimized to satisfy the design constriction; logic capture means for inputting a new logic file partially changing from said old logic file; logic synthesizing means for generating a first intermediate circuit file for storing a first intermediate circuit from said new logic file; circuit updating means for discriminating a common sub-circuit of said old circuit having an equivalent logic function and an uncommon sub-circuit of said first intermediate circuit having an inconsistent logic function from said old circuit file and said first intermediate circuit file; and circuit optimizing means for generating a second intermediate circuit file for storing a second intermediate circuit, by merging the common sub-circuit of said old circuit and the uncommon sub-circuit of said first intermediate circuit and optimizing said uncommon sub-circuit of said second intermediate circuit so as to satisfy the design constriction, wherein said circuit updating means comprises: corresponding flip-flop pair discriminating means for discriminating a pair of flip-flops in said old circuit in said old circuit file and a flip-flop in said first intermediate circuit in said first intermediate circuit file, by using as a search key a name of a primary input/output signal to and from the circuit, and duplicate circuit deleting means for deleting a duplicate circuit contained both in said common sub-circuit of said old circuit file and in said uncommon sub-circuit of said first intermediate circuit file, from said first intermediate circuit, in accordance with an output from said corresponding flip-flop pair discriminating means.

Claim 15

Dependent Claim 286 words

An incremental logic synthesis system for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction, comprising: an old logic file; an old circuit file for storing an old circuit generated from said old logic file and optimized to satisfy the design constriction; logic capture means for inputting a new logic file partially changing from said old logic file; logic synthesizing means for generating a first intermediate circuit file for storing a first intermediate circuit from said new logic file; circuit updating means for discriminating a common sub-circuit of said old circuit having an equivalent logic function and an uncommon sub-circuit of said first intermediate circuit having an inconsistent logic function from said old circuit file and said first intermediate circuit file; and circuit optimizing means for generating a second intermediate circuit file for storing a second intermediate circuit, by merging the common sub-circuit of said old circuit and the uncommon sub-circuit of said first intermediate circuit and optimizing said uncommon sub-circuit of said second intermediate circuit so as to satisfy the design constriction, wherein said circuit updating means comprises: corresponding flip-flop pair discriminating means for discriminating a pair of flip-flops in said old circuit in said old circuit file and a flip-flop in said first intermediate circuit in said first intermediate circuit file, by using as a search key a name of a primary input/output signal to and from the circuit, and duplicate circuit deleting means for deleting a duplicate circuit contained both in said common sub-circuit of said old circuit file and in said uncommon sub-circuit of said first intermediate circuit file, from said first intermediate circuit, in accordance with an output from said corresponding flip-flop pair discriminating means.

Claim 16

Dependent Claim 75 words

An incremental logic synthesis system according to claim 12, wherein said duplicate circuit deleting means includes duplication judging means for discriminating said duplicate circuit by comparing the function of said common sub-circuit of said old circuit of said old circuit file with the function of a sub-circuit of said uncommon sub-circuit of said first intermediate circuit of said first intermediate circuit file, said sub-circuits having the same name of an input signal to said sub-circuits.

Claim 17

Dependent Claim 289 words

An incremental logic synthesis system for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction, comprising: an old logic file; an old circuit file for storing an old circuit generated from said old logic file and optimized to satisfy the design constriction; logic capture means for inputting a new logic file partially changing from said old logic file; logic synthesizing means for generating a first intermediate circuit file for storing a first intermediate circuit from said new logic file; circuit updating means for discriminating a common sub-circuit of said old circuit having an equivalent logic function and an uncommon sub-circuit of said first intermediate circuit having an inconsistent logic function from said old circuit file and said first intermediate circuit file; and circuit optimizing means for generating a second intermediate circuit file for storing a second intermediate circuit, by merging the common sub-circuit of said old circuit and the uncommon sub-circuit of said first intermediate circuit and optimizing said uncommon sub-circuit of said second intermediate circuit so as to satisfy the design constriction, wherein said circuit updating means comprises: corresponding flip-flop pair discriminating means for discriminating a pair of flip-flops in said old circuit in said old circuit file and a flip-flop in said first intermediate circuit in said first intermediate circuit file, by using as a search key a name of a primary input/output signal to and from the circuit, and wherein said circuit optimizing means generates said second intermediate circuit file by merging said common sub-circuit of said old circuit file, said uncommon sub-circuit of said first intermediate circuit file, flip-flops in said first intermediate circuit, and primary input/output terminals of said first intermediate circuit of said first intermediate circuit file.

Claim 18

Dependent Claim 289 words

An incremental logic synthesis system for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction, comprising: an old logic file; an old circuit file for storing an old circuit generated from said old logic file and optimized to satisfy the design constriction; logic capture means for inputting a new logic file partially changing from said old logic file; logic synthesizing means for generating a first intermediate circuit file for storing a first intermediate circuit from said new logic file; circuit updating means for discriminating a common sub-circuit of said old circuit having an equivalent logic function and an uncommon sub-circuit of said first intermediate circuit having an inconsistent logic function from said old circuit file and said first intermediate circuit file; and circuit optimizing means for generating a second intermediate circuit file for storing a second intermediate circuit, by merging the common sub-circuit of said old circuit and the uncommon sub-circuit of said first intermediate circuit and optimizing said uncommon sub-circuit of said second intermediate circuit so as to satisfy the design constriction, wherein said circuit updating means comprises: corresponding flip-flop pair discriminating means for discriminating a pair of flip-flops in said old circuit in said old circuit file and a flip-flop in said first intermediate circuit in said first intermediate circuit file, by using as a search key a name of a primary input/output signal to and from the circuit, and wherein said circuit optimizing means generates said second intermediate circuit file by merging said common sub-circuit of said old circuit file, said uncommon sub-circuit of said first intermediate circuit file, flip-flops in said first intermediate circuit, and primary input/output terminals of said first intermediate circuit of said first intermediate circuit file.

Claim 19

Dependent Claim 273 words

An incremental logic synthesis method for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction, comprising the steps of: inputting an old logic file, an old circuit file for storing an old circuit generated from said old logic file and optimized to satisfy the design constriction, and a new logic file partially changed from said old logic file; generating a first intermediate circuit file for storing a first intermediate circuit from said new logic file; updating by discriminating a common sub-circuit of said old circuit having an equivalent logic function and an uncommon sub-circuit of said first intermediate circuit having an inconsistent logic function from said old circuit file and said first intermediate circuit; and optimizing by generating a second intermediate circuit file for storing a second intermediate circuit, by merging the common sub-circuit of said old circuit and the uncommon sub-circuit of said first intermediate circuit, and optimizing said uncommon sub-circuit of said second intermediate circuit so as to satisfy the design constriction; wherein said updating step comprises the steps of: discriminating a corresponding flip-flop pair by discriminating a pair of flip flops in said old circuit in said old circuit file and a flip-flop in said first intermediate circuit in said first intermediate circuit file, by using as a search key a name of a primary input/output signal to and from the circuit, and deleting a duplicate circuit contained both in said common sub-circuit of said old circuit file and in said uncommon sub-circuit of said first intermediate circuit file, from said first intermediate circuit, in accordance with an output from said corresponding discriminating step.

Claim 20

Dependent Claim 273 words

An incremental logic synthesis method for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction, comprising the steps of: inputting an old logic file, an old circuit file for storing an old circuit generated from said old logic file and optimized to satisfy the design constriction, and a new logic file partially changed from said old logic file; generating a first intermediate circuit file for storing a first intermediate circuit from said new logic file; updating by discriminating a common sub-circuit of said old circuit having an equivalent logic function and an uncommon sub-circuit of said first intermediate circuit having an inconsistent logic function from said old circuit file and said first intermediate circuit; and optimizing by generating a second intermediate circuit file for storing a second intermediate circuit, by merging the common sub-circuit of said old circuit and the uncommon sub-circuit of said first intermediate circuit, and optimizing said uncommon sub-circuit of said second intermediate circuit so as to satisfy the design constriction; wherein said updating step comprises the steps of: discriminating a corresponding flip-flop pair by discriminating a pair of flip flops in said old circuit in said old circuit file and a flip-flop in said first intermediate circuit in said first intermediate circuit file, by using as a search key a name of a primary input/output signal to and from the circuit, and deleting a duplicate circuit contained both in said common sub-circuit of said old circuit file and in said uncommon sub-circuit of said first intermediate circuit file, from said first intermediate circuit, in accordance with an output from said corresponding discriminating step.

Claim 21

Dependent Claim 74 words

An incremental logic synthesis method according to claim 15, wherein said deleting step comprises the step of: judging by discriminating said duplicate circuit by comparing the function of said common sub-circuit of said old circuit of said old circuit file with the function of a sub-circuit of said uncommon sub-circuit of said first intermediate circuit of said first intermediate circuit file, said sub-circuits having the same name of an input signal to said sub-circuits.

Claim 22

Dependent Claim 287 words

An incremental logic synthesis method for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction, comprising the steps of: inputting an old logic file, an old circuit file for storing an old circuit generated from said old logic file and optimized to satisfy the design constriction, and a new logic file partially changing from said old logic file; generating a first intermediate circuit file for storing a first intermediate circuit from said new logic file; updating by discriminating a common sub-circuit of said old circuit having an equivalent logic function and an uncommon sub-circuit of said first intermediate circuit having an inconsistent logic function from said old circuit file and said first intermediate circuit; and optimizing by generating a second intermediate circuit file for storing a second intermediate circuit, by merging the common sub-circuit of said old circuit and the uncommon sub-circuit of said first intermediate circuit, and optimizing said uncommon sub-circuit of said second intermediate circuit so as to satisfy the design constriction; wherein said updating step comprises the step of: discriminating a corresponding flip-flop pair by discriminating a pair of flip flops in said old circuit in said old circuit file and a flip-flop in said first intermediate circuit in said first intermediate circuit file, by using as a search key a name of a primary input/output signal to and from the circuit; and wherein said circuit optimizing step comprises the step of: generating said second intermediate circuit file by merging said common sub-circuit of said old circuit file, said uncommon sub-circuit of said first intermediate circuit file, flip-flops in said first intermediate circuit, and primary input/output terminals of said first intermediate circuit of said first intermediate circuit file.

Claim 23

Dependent Claim 287 words

An incremental logic synthesis method for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction, comprising the steps of: inputting an old logic file, an old circuit file for storing an old circuit generated from said old logic file and optimized to satisfy the design constriction, and a new logic file partially changing from said old logic file; generating a first intermediate circuit file for storing a first intermediate circuit from said new logic file; updating by discriminating a common sub-circuit of said old circuit having an equivalent logic function and an uncommon sub-circuit of said first intermediate circuit having an inconsistent logic function from said old circuit file and said first intermediate circuit; and optimizing by generating a second intermediate circuit file for storing a second intermediate circuit, by merging the common sub-circuit of said old circuit and the uncommon sub-circuit of said first intermediate circuit, and optimizing said uncommon sub-circuit of said second intermediate circuit so as to satisfy the design constriction; wherein said updating step comprises the step of: discriminating a corresponding flip-flop pair by discriminating a pair of flip flops in said old circuit in said old circuit file and a flip-flop in said first intermediate circuit in said first intermediate circuit file, by using as a search key a name of a primary input/output signal to and from the circuit; and wherein said circuit optimizing step comprises the step of: generating said second intermediate circuit file by merging said common sub-circuit of said old circuit file, said uncommon sub-circuit of said first intermediate circuit file, flip-flops in said first intermediate circuit, and primary input/output terminals of said first intermediate circuit of said first intermediate circuit file.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2002-01-04	2002-07-06	2003-01-05	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2006-01-04	2006-07-06	2007-01-05	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2010-01-04	2010-07-06	2011-01-05	$7700.00	Window Closed / Lapsed

Logic synthesis method and system with intermediate circuit files

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