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US5858841A Expired / Lapsed US ⏱️ 0.0 years remaining

ROM device having memory units arranged in three dimensions, and a method of making the same

Assignee: United Microelectronics Corp
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Filing: 1997-11-25
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Granted: 1999-01-12
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Expires: 2017-11-25
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Abstract

Abstract A three-dimensional ROM device includes a silicon substrate having plurality of parallel trenches formed in an upper surface thereof, and a plurality of raised mesa regions. Each trench has a bottom and a pair of sidewalls, and is separated from an adjacent trench by a respective mesa region. A plurality of separated, parallel source/drain regions are provided, including a first and second source/drain region located on respective opposite sides of a respective trench bottom, and a third and fourth source/drain region located on respective opposite sides of a respective raised mesa region. Each source/drain region serves as a bit line. A gate oxide layer is located on the upper surface of the silicon substrate. A plurality of sidewall oxide layers are formed on selected sidewalls and serve as channel barriers. A plurality of silicon nitride layers are formed above selected mesa regions and trench bottoms, and serve as channel barriers. A plurality of gate layers are located over the gate oxide layer and the silicon nitride layers and serve as word lines. A region between any two adjacent source/drain regions comprises a channel region.

Inventors

  • 👤 Chen-Chung Hsu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 12:49
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/50

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 205 words
A method of making a three-dimensionally arranged ROM device, comprising: forming a plurality of parallel trenches in an upper surface of a silicon substrate, each trench having a bottom and a pair of sidewalls, and being separated from an adjacent trench by a respective one of a plurality of raised mesa regions; depositing a silicon nitride layer over the silicon substrate; patterning the silicon nitride layer to expose a portion of the trench bottoms, and a portion of the raised mesa regions, and thereby forming a plurality of silicon nitride layers; using the patterned silicon nitride layers as a mask, and implanting ions in the exposed portions to form a plurality of source/drain regions with the unexposed portions of the trench bottoms and the raised mesa regions forming channel regions; forming a plurality of sidewall oxide layers on the respective trench sidewalls; removing selected sidewall oxide layers for program coding of the ROM device; removing selected silicon nitride layers for program coding of the ROM device; forming a gate oxide layer over the upper surface of the silicon substrate; depositing a polysilicon layer over the silicon nitride layers and gate oxide layer; and patterning the polysilicon layer to form a plurality of polysilicon word lines.
Claim 2
Independent Claim 205 words
A method of making a three-dimensionally arranged ROM device, comprising: forming a plurality of parallel trenches in an upper surface of a silicon substrate, each trench having a bottom and a pair of sidewalls, and being separated from an adjacent trench by a respective one of a plurality of raised mesa regions; depositing a silicon nitride layer over the silicon substrate; patterning the silicon nitride layer to expose a portion of the trench bottoms, and a portion of the raised mesa regions, and thereby forming a plurality of silicon nitride layers; using the patterned silicon nitride layers as a mask, and implanting ions in the exposed portions to form a plurality of source/drain regions with the unexposed portions of the trench bottoms and the raised mesa regions forming channel regions; forming a plurality of sidewall oxide layers on the respective trench sidewalls; removing selected sidewall oxide layers for program coding of the ROM device; removing selected silicon nitride layers for program coding of the ROM device; forming a gate oxide layer over the upper surface of the silicon substrate; depositing a polysilicon layer over the silicon nitride layers and gate oxide layer; and patterning the polysilicon layer to form a plurality of polysilicon word lines.
Claim 3
Dependent Claim 35 words
The method defined in claim 1, wherein said forming a plurality of parallel trenches includes forming the trenches to a depth roughly equal to a width of two source/drain regions and a channel region combined.
Claim 4
Dependent Claim 30 words
The method defined in claim 1, wherein said depositing a silicon nitride layer includes depositing the silicon nitride layer to a thickness between about 1500 Å and about 3000 Å.
Claim 5
Dependent Claim 41 words
The method defined in claim 1, wherein said implanting ions includes implanting arsenic ions having an energy between about 50 KeV and about 100 KeV, and a dosage between about 1×10 14 atoms/cm 2 and about 1×10 16 atoms/cm 2 .
Claim 6
Dependent Claim 41 words
The method defined in claim 1, wherein said implanting ions includes implanting phosphorus ions having an energy between about 20 KeV and about 60 KeV and a dosage between about 1×10 14 atoms/cm 2 and about 1×10 16 atoms/cm 2 .
Claim 7
Dependent Claim 30 words
The method defined in claim 1, wherein said forming a gate oxide layer includes forming the gate oxide layer to a thickness between about 50 Å and about 250 Å.

References Cited (Backward Citations)

US5021355A Cited
US5504025A Cited
US5627091A Cited
US5744393A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-01-11 2002-07-13 2003-01-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-01-11 2006-07-13 2007-01-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-01-11 2010-07-13 2011-01-12 $7700.00 Window Closed / Lapsed

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