US5864486A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for in-system programming of a programmable logic device using a two-wire interface
Assignee: Lattice Semiconductor Corp
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Filing: 1996-05-08
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Granted: 1999-01-26
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Expires: 2016-05-08
Abstract
Abstract Program data generated by the host system to be used in programming one or more associated ISPLDs is converted using a first interface from a parallel data format to a serial data string and then transmitted serially to a second interface. In one embodiment, the first and second interfaces employ Universal Asynchronous Receiver/Transmitter (UARTs). The receiving unit converts the serial program data string to a parallel data byte which is then provided to the programming pins of the ISPLD desired to be programmed. Signals indicative of information relating to the operation of one or more of the ISPLDs associated with the host system may be provided to the host system via pin SDO of the asserted ISPLD. In this manner, embodiments in accordance with the present invention may utilize a two-wire transmission scheme, and thus two-wire interfaces, to facilitate programming of the associated ISPLDs. Having the capability to utilize a two-wire transmission scheme, in turn, allows ISPLDs in accordance with the present invention to be programmed using wired transmission schemes such as, for instance, twisted pair and coaxial, as well as wireless transmission schemes, such as, for instance, radio frequency (RF) and infrared radiation (Ir).
Inventors
- 👤 Andrew S. Deming
- 👤 Daniel T. Gardner
- 👤 James S. Larsen
- 👤 Bertrand Leigh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 20:01
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/34
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
192 words
A system for programming a programmable logic device, comprising: a host system receiving input data and providing output data in parallel; a first interface having a parallel port connected to said host system to receive from said host system said output data and to provide to said host system said input data, said first interface having a serial port, said first interface converting said output data into a first serial bit stream, providing said first serial bit stream for output by said serial port and receiving said input data in a second serial bit stream received at said serial port; and a second interface having a serial port, coupled to receive said first serial bit stream from said serial port of said first interface and to provide said second serial bit stream to said serial port of said first interface, said second interface converting said first serial bit stream received at said serial port of said second interface to parallel input signals of programming pins of said programmable logic device, and converting one or more output signals of said programming pins of said programmable logic device to said second serial bit stream.
Claim 2
Independent Claim
192 words
A system for programming a programmable logic device, comprising: a host system receiving input data and providing output data in parallel; a first interface having a parallel port connected to said host system to receive from said host system said output data and to provide to said host system said input data, said first interface having a serial port, said first interface converting said output data into a first serial bit stream, providing said first serial bit stream for output by said serial port and receiving said input data in a second serial bit stream received at said serial port; and a second interface having a serial port, coupled to receive said first serial bit stream from said serial port of said first interface and to provide said second serial bit stream to said serial port of said first interface, said second interface converting said first serial bit stream received at said serial port of said second interface to parallel input signals of programming pins of said programmable logic device, and converting one or more output signals of said programming pins of said programmable logic device to said second serial bit stream.
Claim 3
Dependent Claim
27 words
The system of claim 1, wherein said serial port of said first interface and said serial port of said second interface are coupled by a coaxial line.
Claim 4
Dependent Claim
28 words
The system of claim 1, wherein said serial port of said first interface and said serial port of said second interface are coupled by a twisted pair line.
Claim 5
Dependent Claim
27 words
The system of claim 1, wherein said serial port of said first interface and said serial port of said second interface are coupled by an ethernet line.
Claim 6
Dependent Claim
20 words
The system of claim 1, wherein said serial ports of said first and second interfaces are coupled by a modem.
Claim 7
Dependent Claim
24 words
The system of claim 1, wherein said first and second serial bits streams are transmitted between first and second interfaces using radio frequency (RF).
Claim 8
Dependent Claim
25 words
The system of claim 1, wherein said first and second serial bit streams are transmitted between said first and second interfaces using infrared radiation (IR).
Claim 9
Dependent Claim
15 words
The system of claim 1, wherein said first interface comprises an asynchronous receiver/transmitter unit (UART).
Claim 10
Independent Claim
154 words
A method for programming a programmable logic device, said method comprising the steps of: generating output programming data and receiving input programming data in a host system, said input and output programming data being provided in parallel form; converting said output programming data into a first serial data stream, and receiving said input programming data from a second serial data stream according to a parallel-to-serial conversion protocol; transmitting said first serial data stream and receiving said second serial data stream through a first interface; receving said first serial data stream and transmitting said second serial data stream through a second interface; converting said first serial data stream into parallel programming data according to a serial-to-parallel conversion protocol and applying said parallel programming data to programming pins of said programmable logic device; and receiving one or more output signals from said programmable logic device and converting said output signals into said second serial data stream.
Claim 11
Independent Claim
154 words
A method for programming a programmable logic device, said method comprising the steps of: generating output programming data and receiving input programming data in a host system, said input and output programming data being provided in parallel form; converting said output programming data into a first serial data stream, and receiving said input programming data from a second serial data stream according to a parallel-to-serial conversion protocol; transmitting said first serial data stream and receiving said second serial data stream through a first interface; receving said first serial data stream and transmitting said second serial data stream through a second interface; converting said first serial data stream into parallel programming data according to a serial-to-parallel conversion protocol and applying said parallel programming data to programming pins of said programmable logic device; and receiving one or more output signals from said programmable logic device and converting said output signals into said second serial data stream.
Claim 12
Dependent Claim
20 words
The method of claim 9, wherein communication between said first and second interfaces are provided over a twisted pair line.
Claim 13
Dependent Claim
19 words
The method of claim 9, wherein communication between said first and second interface are provided over a coaxial line.
Claim 14
Dependent Claim
19 words
The method of claim 9, wherein communication between said first and second interfaces are provided over an ethernet line.
Claim 15
Dependent Claim
19 words
The method of claim 9, wherein communication between said first and second interfaces are provided over radio frequency (RF).
Claim 16
Dependent Claim
17 words
The method of claim 9, wherein communication between said first and second interfaces are provided by infrared
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-25 | 2002-07-27 | 2003-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-25 | 2006-07-27 | 2007-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-25 | 2010-07-27 | 2011-01-26 | $7700.00 | Window Closed / Lapsed |