US5872380A
Expired / Lapsed
US
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Hexagonal sense cell architecture
Assignee: Bell Semiconductor LLC
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Filing: 1995-08-21
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Granted: 1999-02-16
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Expires: 2015-08-21
Abstract
Abstract Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
Inventors
- 👤 Michael D. Rostoker
- 👤 James S. Koford
- 👤 Ranko Scepanovic
- 👤 Edwin R. Jones
- 👤 Gobi R. Padmanahben
- 👤 Ashok K. Kapoor
- 👤 Valerity B. Kudryavtsev
- 👤 Alexander E. Andreev
- 👤 Stanislav V. Aleshin
- 👤 Alexander S. Podkolzin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 16:50
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/392; G06F30/394; G11; G11C; G11C5/00; G11C5/02; G11C5/025; G11C5/06; G11C5/063; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09441; H03K19/0948; H10; H10B; H10B10/00; H10B10/12; H10B12/00; H10D; H10D62/00; H10D62/10; H10D62/117; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10D84/90; H10D84/903; H10D84/907; H10D89/00; H10D89/10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43; H10W20/495
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
216 words
A sense cell, comprising: a triangular structure fabricated on a semiconductor substrate; a first transistor formed as part of the triangular structure, the first transistor having a source region formed at one coner of the triangular structure, the source region of the first transistor being connected to ground, the first transistor having a gate electrode connected to a voltage V G3 ; a second transistor formed as part of the triangular structure, the second transistor having a drain region formed at one coner of the triangular structure, the drain region of the second transistor being connected to a first end of a first resistor, the first resistor having a second end connected to voltage V DD , the second transistor having a gate electrode connected to a voltage V 1 ; a third transistor formed as part of the triangular structure, the third transistor having a drain region formed at one coner of the triangular structure, the drain region of the third transistor being connected to a first end of a second resistor, the second resistor having a second end connected to voltage V DD , the third transistor having a gate electrode connected to a voltage V 2 ; and, the first transistor, the second transistor, and the third transistor having a common source-drain region.
Claim 2
Dependent Claim
216 words
A sense cell, comprising: a triangular structure fabricated on a semiconductor substrate; a first transistor formed as part of the triangular structure, the first transistor having a source region formed at one coner of the triangular structure, the source region of the first transistor being connected to ground, the first transistor having a gate electrode connected to a voltage V G3 ; a second transistor formed as part of the triangular structure, the second transistor having a drain region formed at one coner of the triangular structure, the drain region of the second transistor being connected to a first end of a first resistor, the first resistor having a second end connected to voltage V DD , the second transistor having a gate electrode connected to a voltage V 1 ; a third transistor formed as part of the triangular structure, the third transistor having a drain region formed at one coner of the triangular structure, the drain region of the third transistor being connected to a first end of a second resistor, the second resistor having a second end connected to voltage V DD , the third transistor having a gate electrode connected to a voltage V 2 ; and, the first transistor, the second transistor, and the third transistor having a common source-drain region.
Claim 3
Dependent Claim
78 words
An amplifier structure, comprising: a semiconductor substrate including a triangular doped region having a central common region, and first, second and third regions adjacent to first, second and third vertices of the doped region respectively; first, second and third gates formed between the first, second and third regions respectively and the common region; a first resistance having a first end connected to the first region; and a second resistance having a first end connected to the second region.
Claim 4
Dependent Claim
78 words
An amplifier structure, comprising: a semiconductor substrate including a triangular doped region having a central common region, and first, second and third regions adjacent to first, second and third vertices of the doped region respectively; first, second and third gates formed between the first, second and third regions respectively and the common region; a first resistance having a first end connected to the first region; and a second resistance having a first end connected to the second region.
Claim 5
Dependent Claim
69 words
A structure as in claim 2, in which: the first and second resistances have second ends that are opposite to the first ends thereof respectively; and the structure further comprises: first means for connecting the second ends of the first and second resistances to a first electrical potential; and second means for connecting the third region to a second electrical potential which is different from the first electrical potential.
Claim 6
Dependent Claim
56 words
A structure as in claim 3, further comprising interconnect wiring which is electrically connected to the first, second and third gates, to the second ends of the first and second resistances, and to the third region in a predetermined manner, the interconnect wiring extending in three directions that are angularly displaced from each other by 60°.
Claim 7
Dependent Claim
19 words
A structure as in claim 3, further comprising third means for applying a control signal to the third gate.
Claim 8
Dependent Claim
27 words
A structure as in claim 5, further comprising fourth means for applying an input signal to the first gate and a reference potential to the second gate.
Claim 9
Dependent Claim
22 words
A structure as in claim 5, further comprising fourth means for applying a differential input signal across the first and second gates.
Claim 10
Dependent Claim
137 words
A sense amplifier for a memory cell which has an output, comprising: a semiconductor substrate including a triangular doped region having a central common region, and first, second and third regions adjacent to first, second and third vertices of the doped region respectively; first, second and third gates formed between the first, second and third regions respectively and the common region; a first resistance connected between the first region and a first electrical potential; a second resistance connected between the second region and the first electrical potential; and means for applying a control signal to the third gate; in which: the third region is connected to a second electrical potential that is different from the first electrical potential; and at least one of the first and second gates is connected to said output of the memory cell.
Claim 11
Dependent Claim
137 words
A sense amplifier for a memory cell which has an output, comprising: a semiconductor substrate including a triangular doped region having a central common region, and first, second and third regions adjacent to first, second and third vertices of the doped region respectively; first, second and third gates formed between the first, second and third regions respectively and the common region; a first resistance connected between the first region and a first electrical potential; a second resistance connected between the second region and the first electrical potential; and means for applying a control signal to the third gate; in which: the third region is connected to a second electrical potential that is different from the first electrical potential; and at least one of the first and second gates is connected to said output of the memory cell.
Claim 12
Dependent Claim
55 words
An amplifier as in claim 8, further comprising interconnect wiring which is electrically connected to the first, second and third gates, to external ends of the first and second resistances, and to the third region in a predetermined manner, the interconnect wiring extending in three directions that are angularly displaced from each other by 60°.
Claim 13
Dependent Claim
30 words
An amplifier as in claim 8, in which said output of the memory cell is connected to the first gate and a reference potential is applied to the second gate.
Claim 14
Dependent Claim
27 words
An amplifier as in claim 8, in which said output of the memory cell is a differential output and is applied across the first and second gates.
Claim 15
Dependent Claim
167 words
A microelectronic integrated circuit memory, comprising: a semiconductor substrate; and a plurality of memory devices formed on the substrate, at least one of said memory devices comprising a triangular memory cell having an output, and a sense amplifier for amplifying said output, the sense amplifier including: a triangular doped region having a central common region, and first, second and third regions adjacent to first, second and third vertices of the doped region respectively; first, second and third gates formed between the first, second and third regions respectively and the common region; a first resistance connected between the first region and a first electrical potential; a second resistance connected between the second region and the first electrical potential; and means for applying a control signal to the third gate; in which: the third region is connected to a second electrical potential that is different from the first electrical potential; and at least one of the first and second gates is connected to said output of the memory cell.
Claim 16
Dependent Claim
167 words
A microelectronic integrated circuit memory, comprising: a semiconductor substrate; and a plurality of memory devices formed on the substrate, at least one of said memory devices comprising a triangular memory cell having an output, and a sense amplifier for amplifying said output, the sense amplifier including: a triangular doped region having a central common region, and first, second and third regions adjacent to first, second and third vertices of the doped region respectively; first, second and third gates formed between the first, second and third regions respectively and the common region; a first resistance connected between the first region and a first electrical potential; a second resistance connected between the second region and the first electrical potential; and means for applying a control signal to the third gate; in which: the third region is connected to a second electrical potential that is different from the first electrical potential; and at least one of the first and second gates is connected to said output of the memory cell.
Claim 17
Dependent Claim
55 words
A memory as in claim 12, further comprising interconnect wiring which is electrically connected to the first, second and third gates, to external ends of the first and second resistances, and to the third region in a predetermined manner, the interconnect wiring extending in three directions that are angularly displaced from each other by 60°.
Claim 18
Dependent Claim
30 words
A memory as in claim 12, in which said output of the memory cell is connected to the first gate and a reference potential is applied to the second gate.
Claim 19
Dependent Claim
27 words
A memory as in claim 12, in which said output of the memory cell is a differential output and is applied across the first and second gates.
Claim 20
Dependent Claim
28 words
A memory as in claim 12, in which the memory cell and the sense amplifier are closely packed with additional memory cells and sense amplifiers on the substrate.
Claim 21
Dependent Claim
29 words
A memory as in claim 16, in which the memory cell and the sense amplifier, and the additional memory cells and the additional sense amplifiers define a hexagonal shape.
Claim 22
Dependent Claim
183 words
An electronic system comprising an integrated circuit memory, and additional electronic elements that are operatively connected to the memory, the memory including: a semiconductor substrate; and a plurality of memory devices formed on the substrate, at least one of said memory devices comprising a triangular memory cell having an output, and a sense amplifier for amplifying said output, the sense amplifier including: a triangular doped region having a central common region, and first, second and third regions adjacent to first, second and third vertices of the doped region respectively; first, second and third gates formed between the first, second and third regions respectively and the common region; a first resistance connected between the first region and a first electrical potential; a second resistance connected between the second region and the first electrical potential; and means for applying a control signal to the third gate; in which: the third region is connected to a second electrical potential that is different from the first electrical potential; and at least one of the first and second gates is connected to said output of the memory cell.
Claim 23
Dependent Claim
183 words
An electronic system comprising an integrated circuit memory, and additional electronic elements that are operatively connected to the memory, the memory including: a semiconductor substrate; and a plurality of memory devices formed on the substrate, at least one of said memory devices comprising a triangular memory cell having an output, and a sense amplifier for amplifying said output, the sense amplifier including: a triangular doped region having a central common region, and first, second and third regions adjacent to first, second and third vertices of the doped region respectively; first, second and third gates formed between the first, second and third regions respectively and the common region; a first resistance connected between the first region and a first electrical potential; a second resistance connected between the second region and the first electrical potential; and means for applying a control signal to the third gate; in which: the third region is connected to a second electrical potential that is different from the first electrical potential; and at least one of the first and second gates is connected to said output of the memory cell.
Claim 24
Dependent Claim
15 words
A system as in claim 18, in which the memory comprises a Single-Chip Module (SCM).
Claim 25
Dependent Claim
18 words
A system as in claim 18, comprising a Multi-Chip Module (MCM), the memory being part of the MCM.
Claim 26
Dependent Claim
22 words
A system as in claim 18, further comprising a Board-Level Product (BLP) including a circuit board on which the memory is mounted.
Claim 27
Dependent Claim
19 words
A system as in claim 18, further comprising a box level product including a power supply for the memory.
Claim 28
Dependent Claim
55 words
A system as in claim 18, further comprising interconnect wiring which is electrically connected to the first, second and third gates, to external ends of the first and second resistances, and to the third region in a predetermined manner, the interconnect wiring extending in three directions that are angularly displaced from each other by 60°.
Claim 29
Dependent Claim
30 words
A system as in claim 18, in which said output of the memory cell is connected to the first gate and a reference potential is applied to the second gate.
Claim 30
Dependent Claim
27 words
A system as in claim 18, in which said output of the memory cell is a differential output and is applied across the first and second gates.
Claim 31
Dependent Claim
28 words
A system as in claim 18, in which the memory cell and the sense amplifier are closely packed with additional memory cells and sense amplifiers on the substrate.
Claim 32
Dependent Claim
29 words
A system as in claim 26, in which the memory cell and the sense amplifier, and the additional memory cells and the additional sense amplifiers define a hexagonal shape.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-15 | 2002-08-17 | 2003-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-15 | 2006-08-17 | 2007-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-15 | 2010-08-17 | 2011-02-16 | $7700.00 | Window Closed / Lapsed |