US5877036A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Overlay measuring method using correlation function
Assignee: Renesas Electronics Corp
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Filing: 1997-02-26
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Granted: 1999-03-02
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Expires: 2017-02-26
Abstract
Abstract In a method of manufacturing a semiconductor integrated circuit device, a resist pattern is formed on a lower layer pattern of a semiconductor substrate using a mask. An image signal along a line extending on the lower layer pattern and the resist pattern is generated by an optical system. Based on the image signal, a center position of the resist pattern and a center position of the lower layer pattern are calculated using correlation calculation and an overlay error of the resist pattern to the lower layer pattern is determined. When the overlay error falls within a predetermined range, a next manufacturing process such as an etching process and an ion implantation process to the semiconductor substrate is executed. When the overlay error does not fall within a predetermined range, the resist pattern is removed, and a relative position between the semiconductor substrate and the mask is adjusted. Thereafter, the above steps are repeated.
Inventors
- 👤 Kenji Kawai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:24
CPC Classifications
G; G03; G03F; G03F7/00; G03F7/70; G03F7/70483; G03F7/70605; G03F7/70616; G03F7/70633; H; H10; H10P; H10P74/00
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
102 words
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: forming a resist pattern on a lower layer pattern of a semiconductor substrate using a mask; generating an image signal along a line extending on said lower layer pattern and said resist pattern; calculating an overlay error of said resist pattern to said lower layer pattern from the image signal using a correlation calculation; and performing a next manufacturing process on said semiconductor substrate when said overlay error falls within a predetermined range, wherein said next manufacturing process is one of an etching process and an ion implantation process.
Claim 2
Independent Claim
102 words
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: forming a resist pattern on a lower layer pattern of a semiconductor substrate using a mask; generating an image signal along a line extending on said lower layer pattern and said resist pattern; calculating an overlay error of said resist pattern to said lower layer pattern from the image signal using a correlation calculation; and performing a next manufacturing process on said semiconductor substrate when said overlay error falls within a predetermined range, wherein said next manufacturing process is one of an etching process and an ion implantation process.
Claim 3
Dependent Claim
97 words
A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said calculating step includes: calculating a center position of said lower layer pattern using the correlation calculation based on a first signal portion of said image signal indicative of edge portions of said lower layer pattern; calculating a center position of said resist pattern from a second signal portion of said image signal indicative of edge portions of said resist pattern; and calculating said overlay error from said center position of said lower layer pattern and said center position of said resist pattern.
Claim 4
Dependent Claim
114 words
A method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein said step of calculating a center position of said lower layer pattern includes: generating new waveform portions having the same shapes as waveform portions corresponding to the edge portions of said lower layer pattern on positions moved in directions opposite to each other by a same distance with respect to positions of the waveform portions corresponding to the edge portions of said lower layer pattern; synthesizing the generated new waveform portions and said first signal portion to produce a synthesized signal; and performing the correlation calculation to the synthesized signal to calculate said center position of said lower layer pattern.
Claim 5
Dependent Claim
68 words
A method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein said step of calculating a center position of said lower layer pattern includes: performing the correlation calculation to said lower layer pattern signal to calculate said center position of said lower layer pattern without generating any new waveform portions when the waveform portions corresponding to edge portions of said lower layer pattern are similar.
Claim 6
Dependent Claim
156 words
A method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein said step of calculating a center position of said lower layer pattern includes: determining whether waveform portions of said image signal corresponding to the edge portions of said lower layer pattern are similar; generating new waveform portions having the same shapes as the waveform portions corresponding to the edge portions of said lower layer pattern on positions moved in directions opposite to each other by a same distance with respect to positions of the waveform portions corresponding to the edge portions of said lower layer pattern, when it is determined that the waveform portions corresponding to the edge portions of said lower layer pattern are not similar; synthesizing the generated new waveform portions and said first signal portion to produce a synthesized signal; and performing the correlation calculation on the synthesized signal to calculate said center position of said lower layer pattern.
Claim 7
Dependent Claim
67 words
A method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein said step of calculating a center position of said lower layer pattern includes: performing the correlation calculation to said first signal portion to calculate said center position of said lower layer pattern without generating any new waveform portions when the waveform portions corresponding to edge portions of said lower layer pattern are similar.
Claim 8
Dependent Claim
87 words
A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said calculating step includes: separating a lower layer pattern signal and a resist pattern signal from said image signal; calculating a center position of said lower layer pattern from said lower layer pattern signal using the correlation calculation; calculating a center position of said resist pattern from said resist pattern signal; and calculating said overlay error from said center position of said lower layer pattern and said center position of said resist pattern.
Claim 9
Dependent Claim
131 words
A method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein said step of calculating a center position of said lower layer pattern includes: generating new waveform portions having the same shapes as waveform portions corresponding to edge portions of said lower layer pattern on positions moved in directions opposite to each other by a same distance with respect to positions of the waveform portions corresponding to the edge portions of said lower layer pattern, when the waveform portions corresponding to the edge portions of said lower layer pattern are not similar; synthesizing the generated new waveform portions and said lower layer pattern signal to produce a synthesized signal; and performing the correlation calculation to the synthesized signal to calculate said center position of said lower layer pattern.
Claim 10
Dependent Claim
68 words
A method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein said step of calculating a center position of said lower layer pattern includes: performing the correlation calculation to said lower layer pattern signal to calculate said center position of said lower layer pattern without generating any new waveform portions when the waveform portions corresponding to edge portions of said lower layer pattern are similar.
Claim 11
Dependent Claim
69 words
A method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising the steps of: removing said resist pattern when said overlay error does not fall within said predetermined range; relatively moving said semiconductor substrate and said mask; and repeating said step of forming a resist pattern, said step of generating an image signal and said step of calculating an overlay error of said resist pattern.
Claim 12
Independent Claim
121 words
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: forming a resist pattern on a lower layer pattern of a semiconductor substrate using a mask; generating an image signal along a line extending on said lower layer pattern and said resist pattern; calculating a center position of said resist pattern and a center position of said lower layer pattern using a correlation calculation based on said image signal to determine an overlay error of said resist pattern to said lower layer pattern; and performing a next manufacturing process on said semiconductor substrate when said overlay error falls within a predetermined range, wherein said next manufacturing process is one of an etching process and an ion implantation process.
Claim 13
Independent Claim
121 words
A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: forming a resist pattern on a lower layer pattern of a semiconductor substrate using a mask; generating an image signal along a line extending on said lower layer pattern and said resist pattern; calculating a center position of said resist pattern and a center position of said lower layer pattern using a correlation calculation based on said image signal to determine an overlay error of said resist pattern to said lower layer pattern; and performing a next manufacturing process on said semiconductor substrate when said overlay error falls within a predetermined range, wherein said next manufacturing process is one of an etching process and an ion implantation process.
Claim 14
Dependent Claim
97 words
A method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein said calculating step includes: calculating a center position of said lower layer pattern using the correlation calculation based on a first signal portion of said image signal indicative of edge portions of said lower layer pattern; calculating a center position of said resist pattern from a second signal portion of said image signal indicative of edge portions of said resist pattern; and calculating said overlay error from said center position of said lower layer pattern and said center position of said resist pattern.
Claim 15
Dependent Claim
114 words
A method of manufacturing a semiconductor integrated circuit device according to claim 12, wherein said step of calculating a center position of said lower layer pattern includes: generating new waveform portions having the same shapes as waveform portions corresponding to the edge portions of said lower layer pattern on positions moved in directions opposite to each other by a same distance with respect to positions of the waveform portions corresponding to the edge portions of said lower layer pattern; synthesizing the generated new waveform portions and said first signal portion to produce a synthesized signal; and performing the correlation calculation to the synthesized signal to calculate said center position of said lower layer pattern.
Claim 16
Dependent Claim
68 words
A method of manufacturing a semiconductor integrated circuit device according to claim 12, wherein said step of calculating a center position of said lower layer pattern includes: performing the correlation calculation to said lower layer pattern signal to calculate said center position of said lower layer pattern without generating any new waveform portions when the waveform portions corresponding to edge portions of said lower layer pattern are similar.
Claim 17
Dependent Claim
157 words
A method of manufacturing a semiconductor integrated circuit device according to claim 12, wherein said step of calculating a center position of said lower layer pattern includes: determining whether the waveform portions of said image signal corresponding to the edge portions of said lower layer pattern are similar; generating new waveform portions having the same shapes as the waveform portions corresponding to the edge portions of said lower layer pattern on positions moved in directions opposite to each other by a same distance with respect to positions of the waveform portions corresponding to the edge portions of said lower layer pattern, when it is determined that the waveform portions corresponding to the edge portions of said lower layer pattern are not similar; synthesizing the generated new waveform portions and said first signal portion to produce a synthesized signal; and performing the correlation calculation on the synthesized signal to calculate said center position of said lower layer pattern.
Claim 18
Dependent Claim
67 words
A method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein said step of calculating a center position of said lower layer pattern includes: performing the correlation calculation to said first signal portion to calculate said center position of said lower layer pattern without generating any new waveform portions when the waveform portions corresponding to edge portions of said lower layer pattern are similar.
Claim 19
Dependent Claim
87 words
A method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein said calculating step includes: separating a lower layer pattern signal and a resist pattern signal from said image signal; calculating a center position of said lower layer pattern from said lower layer pattern signal using the correlation calculation; calculating a center position of said resist pattern from said resist pattern signal; and calculating said overlay error from said center position of said lower layer pattern and said center position of said resist pattern.
Claim 20
Dependent Claim
131 words
A method of manufacturing a semiconductor integrated circuit device according to claim 17, wherein said step of calculating a center position of said lower layer pattern includes: generating new waveform portions having the same shapes as waveform portions corresponding to edge portions of said lower layer pattern on positions moved in directions opposite to each other by a same distance with respect to positions of the waveform portions corresponding to the edge portions of said lower layer pattern, when the waveform portions corresponding to the edge portions of said lower layer pattern are not similar; synthesizing the generated new waveform portions and said lower layer pattern signal to produce a synthesized signal; and performing the correlation calculation to the synthesized signal to calculate said center position of said lower layer pattern.
Claim 21
Dependent Claim
68 words
A method of manufacturing a semiconductor integrated circuit device according to claim 18, wherein said step of calculating a center position of said lower layer pattern includes: performing the correlation calculation to said lower layer pattern signal to calculate said center position of said lower layer pattern without generating any new waveform portions when the waveform portions corresponding to edge portions of said lower layer pattern are similar.
Claim 22
Dependent Claim
69 words
A method of manufacturing a semiconductor integrated circuit device according to claim 11, further comprising the steps of: removing said resist pattern when said overlay error does not fall within a predetermined range; relatively moving said semiconductor substrate and said mask; and repeating said step of forming a resist pattern, said step of generating an image signal and said step of calculating an overlay error of said resist pattern.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-01 | 2002-08-31 | 2003-03-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-01 | 2006-08-31 | 2007-03-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-01 | 2010-08-31 | 2011-03-02 | $7700.00 | Window Closed / Lapsed |