Nonvolatile memory device having a program-assist plate

Claim 2

A nonvolatile memory device comprising: an array of nonvolatile memory cells formed on a semiconductor substrate the memory cells having sidewall insulators, and lightly doped drain and source regions formed in the substrate; an insulating layer formed over said array of nonvolatile memory cells; and an electrically conductive program-assist plate formed over said insulating layer and selectively coupled to one or more applied voltages.

Claim 3

A nonvolatile memory device as in claim 1, wherein each said nonvolatile memory cell further comprises a gate insulation layer formed on said substrate, a floating gate formed on said gate insulation layer, an interdielectric layer formed on said floating gate, and a control gate formed on said interdielectric layer.

Claim 4

A nonvolatile memory device as in claim 2, wherein: said insulating layer comprises one selected from a group consisting of an oxide film, a nitride film, an oxynitride film, and a composite film thereof; and said program-assist plate comprises one selected from a group consisting of polysilicon and polycide.

Claim 5

A nonvolatile memory device as in claim 3, wherein said array of nonvolatile memory cells comprises a NAND array.

Claim 6

A nonvolatile memory device as in claim 3, wherein said array of nonvolatile memory cells comprises a NOR array.

Claim 7

A nonvolatile memory device as in claim 3, wherein said array of nonvolatile memory cells comprises an AND array.

Claim 8

A nonvolatile memory device as in claim 3, wherein said array of nonvolatile memory cells comprises a DINOR array.

Claim 9

A nonvolatile memory device comprising: a NOR or DINOR array of nonvolatile memory cells formed on a semiconductor substrate, said array divided into a plurality of blocks of nonvolatile memory cells; an insulating layer formed over said blocks of nonvolatile memory cells; and a plurality of electrically conductive program-assist plates, each said program-assist plate formed over said insulating layer and above one of the blocks of nonvolatile memory cells, and selectively coupled to one or more applied voltages.

Claim 10

A nonvolatile memory device comprising: a NOR or DINOR array of nonvolatile memory cells formed on a semiconductor substrate, said array divided into a plurality of blocks of nonvolatile memory cells; an insulating layer formed over said blocks of nonvolatile memory cells; and a plurality of electrically conductive program-assist plates, each said program-assist plate formed over said insulating layer and above one of the blocks of nonvolatile memory cells, and selectively coupled to one or more applied voltages.

Claim 11

A nonvolatile memory device as in claim 8, wherein each said nonvolatile memory cell comprises a gate insulation layer formed on said substrate, a floating gate formed on said gate insulation layer, an interdielectric layer formed on said floating gate, and a control gate formed on said interdielectric layer.

Claim 12

A nonvolatile memory device as in claim 9, wherein: said insulating layer comprises one selected from a group consisting of an oxide film, a nitride film, an oxynitride film, and a composite film thereof; and said program-assist plate comprises one selected from a group consisting of polysilicon and polycide.

Claim 13

A nonvolatile memory device as in claim 10, wherein said array of nonvolatile memory cells is a NAND array comprising at least one NAND string coupled to a pair of select transistors, and wherein the program-assist plate is formed over the NAND strings but not over the select transistors.

Claim 14

A nonvolatile memory device as in claim 11, wherein each of the memory cells comprises a sidewall insulator, and lightly doped drain and source regions formed in the substrate.

Claim 15

A nonvolatile memory device as in claim 10, wherein said array of nonvolatile memory cells is an AND array comprising at least one AND string coupled to a pair of select transistors, and wherein the program-assist plate is formed over the AND strings but not over the select transistors.

Claim 16

A nonvolatile memory device as in claim 13, wherein each of the memory cells comprises a sidewall insulator, and lightly doped drain and source regions formed in the substrate.

Claim 17

A nonvolatile memory device having an array of blocks, each said block comprising: a plurality of substantially parallel strings, each said string having a plurality of transistors electrically connected source-to-drain in series with a source select transistor at an end of said string, a string select transistor at another end of said string, and a plurality of cell transistors arranged in said string therebetween, each said string select transistor connected to a bitline and each said source select transistor connected to a source line; each said cell transistor having a floating gate and a control gate with an interdielectric layer therebetween, a sidewall insulating layer, and lightly doped drain and source regions; a string select line connected to a gate of each string select transistor; a source select line connected to a gate of each source select transistor; a plurality of substantially parallel wordlines arranged substantially perpendicular to said plurality of strings, each said wordline associated with a different one of said cell transistors in each said string, and connected to said control gate of said associated cell transistor in each said string; an insulating filh having a predetermined thickness formed over said cell transistors in said block; and an electrically conductive program-assist plate formed on said insulating film and selectively coupled to one or more applied voltages.

Claim 18

A nonvolatile memory device having an array of blocks, each said block comprising: a plurality of substantially parallel strings, each said string having a plurality of transistors electrically connected source-to-drain in series with a source select transistor at an end of said string, a string select transistor at another end of said string, and a plurality of cell transistors arranged in said string therebetween, each said string select transistor connected to a bitline and each said source select transistor connected to a source line; each said cell transistor having a floating gate and a control gate with an interdielectric layer therebetween, a sidewall insulating layer, and lightly doped drain and source regions; a string select line connected to a gate of each string select transistor; a source select line connected to a gate of each source select transistor; a plurality of substantially parallel wordlines arranged substantially perpendicular to said plurality of strings, each said wordline associated with a different one of said cell transistors in each said string, and connected to said control gate of said associated cell transistor in each said string; an insulating filh having a predetermined thickness formed over said cell transistors in said block; and an electrically conductive program-assist plate formed on said insulating film and selectively coupled to one or more applied voltages.

Claim 19

A nonvolatile memory device as in claim 15, wherein: said insulating film comprises one selected from a group consisting of an oxide film, a nitride film, an oxynitride film, and a composite film thereof; and said program-assist plate comprises one selected from a group consisting of polysilicon and polycide.

Claim 20

A nonvolatile memory device as in claim 16, wherein said predetermined thickness of said insulating film above said control gates is greater than said predetermined thickness on said sidewalls of said cell transistors.

Claim 21

A nonvolatile memory device as in claim 16, wherein said predetermined thickness of said insulating film is approximately 30 nm.

Claim 22

A nonvolatile memory device having an array of blocks, each said block comprising: a plurality of substantially parallel strings, each said string having a plurality of transistors electrically connected source-to-drain in series with a source select transistor at an end of said string, a string select transistor at another end of said string, and a plurality of cell transistors arranged in said string therebetween, each said string select transistor connected to a bitline and each said source select transistor connected to a source line; each said cell transistor having a floating gate and a control gate with an interdielectric layer therebetween, and sidewalls; a string select line connected to a gate of each string select transistor; a source select line connected to a gate of each source select transistor; a plurality of substantially parallel wordlines arranged substantially perpendicular to said plurality of strings, each said wordline associated with a different one of said cell transistors in each said string, and connected to said control gate of said associated cell transistor in each said string; an insulating film having a predetermined thickness formed over said plurality of strings in said block; and an electrically conductive program-assist plate formed on said insulating film over the plurality of cell transistors in the block but not over the select transistors, and selectively coupled to one or more applied voltages.

Claim 23

A nonvolatile memory device having an array of blocks, each said block comprising: a plurality of substantially parallel strings, each said string having a plurality of transistors electrically connected source-to-drain in series with a source select transistor at an end of said string, a string select transistor at another end of said string, and a plurality of cell transistors arranged in said string therebetween, each said string select transistor connected to a bitline and each said source select transistor connected to a source line; each said cell transistor having a floating gate and a control gate with an interdielectric layer therebetween, and sidewalls; a string select line connected to a gate of each string select transistor; a source select line connected to a gate of each source select transistor; a plurality of substantially parallel wordlines arranged substantially perpendicular to said plurality of strings, each said wordline associated with a different one of said cell transistors in each said string, and connected to said control gate of said associated cell transistor in each said string; an insulating film having a predetermined thickness formed over said plurality of strings in said block; and an electrically conductive program-assist plate formed on said insulating film over the plurality of cell transistors in the block but not over the select transistors, and selectively coupled to one or more applied voltages.

Claim 24

A nonvolatile memory device as in claim 19, wherein: said insulating film comprises one selected from a group consisting of an oxide film, a nitride film, an oxynitride film, and a composite film thereof; and said program-assist plate comprises one selected from a group consisting of polysilicon and polycide.

Claim 25

A nonvolatile memory device as in claim 20, wherein said predetermined thickness of said insulating film above said control gates is greater than said predetermined thickness on said sidewalls of said cell transistors.

Claim 26

A nonvolatile memory device as in claim 20, wherein said cell transistors further comprise: a sidewall insulating layer on said sidewalls; and a lightly doped drain source and drain regions.

Claim 27

A nonvolatile memory device as in claim 20, wherein said predetermined thickness of said insulating film is approximately 30 nm.

Claim 28

A nonvolatile memory device as in claim 22, wherein said predetermined thickness of said insulating film is approximately 30 nm.