Dynamic allocation of queue space using counters

Claim 2

A computer system having a processor that creates request packets to access memory and creates response packets that satisfy queries made by the system, the system comprising: a dynamically allocable buffer space for storing and routing the request packets and the response packets; and an arbiter for receiving the request packets and the response packets from the processor, and for making determinations whether to send the request packets and the response packets to the buffer space; wherein said determinations are made in part, under control of: a request counter that stores a number value representing a total number of request packets currently stored in the buffer space; a response counter that stores a number value representing a total number of response packets currently stored in the buffer space; a total counter that stores a number value representing a total number of both request packets and response packets currently stored in the buffer space; a request limit value representing a maximum number of request packets that is capable of being stored in the buffer space; a response limit value representing a maximum number of response packets that is capable of being stored in the buffer space; and a total limit value representing a maximum number of both request packets and response packets that is capable of being stored in the buffer space.

Claim 3

The computer system of claim 1, wherein: the request limit, the response limit, and the total limit are alterable by software commands.

Claim 4

The computer system of claim 2, wherein: the request limit, the response limit, and the total limit are each stored in a respective register.

Claim 5

The computer system of claim 1, wherein: the arbiter compares the request limit with the request counter and compares the total limit with the total counter to determine whether to send the request packet to the buffer space; if the request limit is greater than the request counter, and if the total limit is greater than the total counter, then the arbiter will send the request packet and increment both the request counter and the total counter; if the request limit is not greater than the request counter, then the arbiter compares the response limit with the response counter and compares the total limit with the total counter to determine whether to send the response packet to the buffer space; and if the total limit is not greater than the total counter, then the arbiter will send neither the request packet nor the response packet until the total limit is greater than the total counter.

Claim 6

The computer system of claim 4, wherein: the buffer space transmits the request packet to a location in the system after receiving the request packet from the arbiter, and then relays transmission information to the arbiter; and the arbiter receives the transmission information and decrements the request counter and the total counter.

Claim 7

The computer system of claim 1, wherein: the arbiter compares the request limit with the request counter and compares the total limit with the total counter to determine whether to send the request packet to the buffer space; if the request limit is greater than the request counter, and if the total limit is greater than the total counter, then the arbiter will send the request packet and increment both the request counter and the total counter; if the request limit is not greater than the request counter, then the arbiter will not send the request packet; and if the total limit is not greater than the total counter, then the arbiter will not send the request packet.

Claim 8

The computer system of claim 6, wherein: the buffer space transmits the request packet to a location in the system after receiving the request packet from the arbiter, and then relays transmission information to the arbiter; and the arbiter receives the transmission information and decrements the request counter and the total counter.

Claim 9

The computer system of claim 1, wherein: the arbiter compares the response limit with the response counter and compares the total limit with the total counter to determine whether to send the response packet to the buffer space; if the response limit is greater than the response counter, and if the total limit is greater than the total counter, then the arbiter will send the response packet and increment both the response counter and the total counter; if the response limit is not greater than the response counter, then the arbiter compares the request limit with the request counter and compares the total limit with the total counter to determine whether to send the request packet to the buffer space; and if the total limit is not greater than the total counter, then the arbiter will send neither the request packet nor the response packet until the total limit is greater than the total counter.

Claim 10

The computer system of claim 8, wherein: the buffer space transmits the response packet to a location in the system after receiving the response packet from the arbiter, and then relays transmission information to the arbiter; and the arbiter receives the transmission information and decrements the response counter and the total counter.

Claim 11

The computer system of claim 1, wherein: the arbiter compares the response limit with the response counter and compares the total limit with the total counter to determine whether to send the response packet to the buffer space; if the response limit is greater than the response counter, and if the total limit is greater than the total counter, then the arbiter will send the response packet and increment both the response counter and the total counter; if the response limit is not greater than the response counter, then the arbiter will not send the response packet; and if the total limit is not greater than the total counter, then the arbiter will not send the response packet.

Claim 12

The computer system of claim 10, wherein: the buffer space transmits the response packet to a location in the system after receiving the response packet from the arbiter, and then relays transmission information to the arbiter; and the arbiter receives the transmission information and decrements the response counter and the total counter.

Claim 13

The computer system of claim 1, wherein: the request limit is 8; the response limit is 8; and the total limit is 10.

Claim 14

The computer system of claim 1, wherein: a reserved request space of the buffer space is equal to the total limit minus the response limit; a reserved response space of the buffer space is equal to the total limit minus the request limit; and a dynamically allocable space of the buffer space is equal to the request limit plus the response limit minus the total limit.

Claim 15

The computer system of claim 13, wherein: the request limit is 8; the response limit is 8; the total limit is 10; the reserved request space is 2; the reserved response space is 2; and the dynamically allocable space is 6.

Claim 16

The computer system of claim 13, wherein: the request limit is 9; the response limit is 10; the total limit is 10; the reserved request space is 0; the reserved response space is 1; and the dynamically allocable space is 9.

Claim 17

The computer system of claim 13, wherein: the request limit is 7; the response limit is 7; the total limit is 10; the reserved request space is 3; the reserved response space is 3; and the dynamically allocable space is 4.

Claim 18

A multi-processor computer system having a dynamically allocable buffer space for handling request packets and response packets, the computer system comprising a plurality of nodes interconnected by a plurality of SCI rings, a node of the plurality of nodes comprising: at least one processor that creates request packets to access memory and creates response packets that satisfy queries made by the system; a memory for storing data; at least one processor agent for dispatching packets, and comprising: an arbiter that receives the request packets and the response packets from the processor and makes determinations whether to send the request packets and the response packets to the buffer space; at least one memory agent for controlling access to the memory, that receives the packet from the processor agent and determines a target location for that packet; and at least one crossbar for routing the response packets and the request packets between the processor agent and the memory agent, and comprises the buffer space; and wherein when the memory agent determines that the target location is within the node, then the memory agent delivers the packet to the location; and when the memory agent determines that the target location is located on a remote node, then the memory agent forwards the packet to the SCI controller, the SCI controller sends the packet to the remote node through the SCI ring, comprising: a request counter that stores a number value representing a total number of request packets currently stored in the buffer space; a response counter that stores a number value representing a total number of response packets currently stored in the buffer space; a total counter that stores a number value representing a total number of both request packets and response packets currently stored in the buffer space; a request limit is a number value representing a maximum number of request packets that is capable of being stored in the buffer space; a response limit is a number value representing a maximum number of response packets that is capable of being stored in the buffer space; and a total limit is a number value representing a maximum number of both request packets and response packets that is capable of being stored in the buffer space.

Claim 19

A multi-processor computer system having a dynamically allocable buffer space for handling request packets and response packets, the computer system comprising a plurality of nodes interconnected by a plurality of SCI rings, a node of the plurality of nodes comprising: at least one processor that creates request packets to access memory and creates response packets that satisfy queries made by the system; a memory for storing data; at least one processor agent for dispatching packets, and comprising: an arbiter that receives the request packets and the response packets from the processor and makes determinations whether to send the request packets and the response packets to the buffer space; at least one memory agent for controlling access to the memory, that receives the packet from the processor agent and determines a target location for that packet; and at least one crossbar for routing the response packets and the request packets between the processor agent and the memory agent, and comprises the buffer space; and wherein when the memory agent determines that the target location is within the node, then the memory agent delivers the packet to the location; and when the memory agent determines that the target location is located on a remote node, then the memory agent forwards the packet to the SCI controller, the SCI controller sends the packet to the remote node through the SCI ring, comprising: a request counter that stores a number value representing a total number of request packets currently stored in the buffer space; a response counter that stores a number value representing a total number of response packets currently stored in the buffer space; a total counter that stores a number value representing a total number of both request packets and response packets currently stored in the buffer space; a request limit is a number value representing a maximum number of request packets that is capable of being stored in the buffer space; a response limit is a number value representing a maximum number of response packets that is capable of being stored in the buffer space; and a total limit is a number value representing a maximum number of both request packets and response packets that is capable of being stored in the buffer space.

Claim 20

The computer system of claim 17, wherein: the request limit, the response limit, and the total limit are alterable by software commands.

Claim 21

The computer system of claim 17, wherein: the arbiter compares the request limit with the request counter and compares the total limit with the total counter to determine whether to send the request packet to the buffer space; if the request limit is greater than the request counter, and if the total limit is greater than the total counter, then the arbiter will send the request packet and increment both the request counter and the total counter; if the request limit is not greater than the request counter, then the arbiter compares the response limit with the response counter and compares the total limit with the total counter to determine whether to send the response packet to the buffer space; and if the total limit is not greater than the total counter, then the arbiter will send neither the request packet nor the response packet until the total limit is greater than the total counter.

Claim 22

The computer system of claim 19, wherein: the buffer space transmits the request packet to a location in the system after receiving the request packet from the arbiter, and then relays transmission information to the arbiter; and the arbiter receives the transmission information and decrements the request counter and the total counter.

Claim 23

The computer system of claim 17, wherein: the arbiter compares the response limit with the response counter and compares the total limit with the total counter to determine whether to send the response packet to the buffer space; if the response limit is greater than the response counter, and if the total limit is greater than the total counter, then the arbiter will send the response packet and increment both the response counter and the total counter; if the response limit is not greater than the response counter, then the arbiter compares the request limit with the request counter and compares the total limit with the total counter to determine whether to send the request packet to the buffer space; and if the total limit is not greater than the total counter, then the arbiter will send neither the request packet nor the response packet until the total limit is greater than the total counter.

Claim 24

The computer system of claim 21, wherein: the buffer space transmits the response packet to a location in the system after receiving the response packet from the arbiter, and then relays transmission information to the arbiter; and the arbiter receives the transmission information and decrements the response counter and the total counter.

Claim 25

The computer system of claim 17, wherein: a reserved request space of the buffer space is equal to the total limit minus the response limit; a reserved response space of the buffer space is equal to the total limit minus the request limit; and a dynamically allocable space of the buffer space is equal to the request limit plus the response limit minus the total limit.

Claim 26

The computer system of claim 23, wherein: the request limit is 8; the response limit is 8; the total limit is 10; the reserved request space is 2; the reserved response space is 2; and the dynamically allocable space is 6.

Claim 27

The computer system of claim 23, wherein: the request limit is 9; the response limit is 10; the total limit is 10; the reserved request space is 0; the reserved response space is 1; and the dynamically allocable space is 9.

Claim 30

The method of claim 26, further comprising the step of: sending the request packets to a location in the system.

Claim 31

The method of claim 26, further comprising the step of: altering the request limit, the response limit, and the total limit, to re-configure the system.

Claim 32

The method of claim 26, wherein the step of determining whether to send the request packets and the response packets to the buffer space, further comprises the steps of: determining whether to send the request packet to the buffer space, comprising the steps of: comparing the request limit with the request count; comparing the total limit with the total count; sending the request packet to the buffer space if the request limit is greater than the request count, and if the total limit is greater than the total count; incrementing both the request count and the total count; holding the request packet if the request limit is not greater than the request count; and holding the request packet if the total limit is not greater than the total count.

Claim 33

The method of claim 29, further comprising the steps of: transmitting the request packet out of the buffer space and to a location in the system; and decrementing both the request count and the total count.

Claim 34

The method of claim 26, wherein the step of determining whether to send the request packets and the response packets to the buffer space, further comprises the steps of: determining whether to send the response packet to the buffer space, comprising the steps of: comparing the response limit with the response count; comparing the total limit with the total count; sending the response packet to the buffer space if the response limit is greater than the response count, and if the total limit is greater than the total count; incrementing both the response count and the total count; holding the response packet if the response limit is not greater than the response count; and holding the response packet if the total limit is not greater than the total count.

Claim 35

The method of claim 31, further comprising the steps of: transmitting the response packet out of the buffer space and to a location in the system; and decrementing both the response count and the total count.