US5883827A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for reading/writing data in a memory system including programmable resistors
Assignee: Round Rock Research LLC
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Filing: 1996-08-26
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Granted: 1999-03-16
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Expires: 2016-08-26
Abstract
Abstract The present invention relates to circuitry and a related method to reliably write data to an array of programmable resistance elements by selectively applying pulses of a sufficient level to impart either a first (high) or second (low) resistance state to selected programmable resistance elements to store either a binary "1" or "0", respectively. Data is then read from the array by supplying currents though the selected programmable resistance element and a fixed resistive element. A comparison of the resulting voltages on nodes coupled to these resistive elements will indicate whether the resistance value of the programmable resistance element is at a high or low state, i.e., a binary "1" or "0". Further, a shunt circuit is coupled to the selected column lines of the array to protect the programmable resistance elements from excessive spurious or noise currents, which can erroneously program the programmable resistance elements.
Inventors
- 👤 Donald M. Morgan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 17:27
CPC Classifications
G; G11; G11C; G11C13/00; G11C13/0002; G11C13/0004; G11C13/0021; G11C13/004; G11C13/0069; G11C2013/0047; G11C2013/0054; G11C2013/0078; G11C2213/00; G11C2213/70; G11C2213/79
Claims Analysis
Total Claims: 104
Claim 1
Independent Claim
160 words
A memory system comprising: an array of programmable resistance elements, each of which being programmable to one of a first resistance state and a second resistance state, wherein said programmable resistance elements are arranged in a plurality of columns and rows in said array; a comparison circuit coupled to said array of programmable resistance elements, said comparison circuit adapted to compare sense signals developed by said programmable resistance elements and reference signals, and to generate read-out signals in response to said comparisons; a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in said columns: a plurality of row lines respectively coupled to pluralities of programmable resistance elements arranged in said rows; a column decoder circuit coupled to select one of said column lines; and a row decoder circuit coupled to select one of said row lines, thereby selecting one of said programmable resistance elements coupled to said selected column line and said selected row line.
Claim 2
Dependent Claim
160 words
A memory system comprising: an array of programmable resistance elements, each of which being programmable to one of a first resistance state and a second resistance state, wherein said programmable resistance elements are arranged in a plurality of columns and rows in said array; a comparison circuit coupled to said array of programmable resistance elements, said comparison circuit adapted to compare sense signals developed by said programmable resistance elements and reference signals, and to generate read-out signals in response to said comparisons; a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in said columns: a plurality of row lines respectively coupled to pluralities of programmable resistance elements arranged in said rows; a column decoder circuit coupled to select one of said column lines; and a row decoder circuit coupled to select one of said row lines, thereby selecting one of said programmable resistance elements coupled to said selected column line and said selected row line.
Claim 3
Dependent Claim
38 words
A memory system in accordance with claim 1, wherein said column decoder has a plurality of outputs respectively corresponding to said plurality of column lines, one of said plurality of outputs operable to select said selected column line.
Claim 4
Dependent Claim
97 words
A memory system in accordance with claim 2, wherein said column decoder circuit further comprises: a plurality of driver circuits respectively coupled to said plurality of outputs of said column decoder, one of said plurality of driver circuits coupled to said one output and generating a first potential signal operable to select said selected column line, remaining ones of said plurality of driver circuits receiving a second potential signal and supplying, in response thereto, a third potential signal to said remaining outputs of said column decoder, thereby deselecting said column lines other than said selected column line.
Claim 5
Dependent Claim
26 words
A memory system in accordance with claim 3, wherein a magnitude of said first potential signal being greater than a magnitude of said second potential signal.
Claim 6
Dependent Claim
19 words
A memory system in accordance with claim 3, wherein each said plurality of driver circuits includes an inverter circuit.
Claim 7
Dependent Claim
147 words
A memory system in accordance with claim 3, wherein each of said plurality of driver circuits respectively includes: a n-channel MOS transistor having a source electrode for connection to a ground potential, a gate electrode for receiving an input signal, and a drain electrode coupled to said output node of said first driver circuit; a first p-channel MOS transistor having a drain electrode coupled to said gate electrode of said n-channel transistor, a source electrode coupled to a supply potential, and a gate electrode coupled to said driver circuit output; and a second p-channel MOS transistor having a drain electrode coupled to a drain electrode of said n-channel MOS transistor, a source electrode coupled to said supply potential, and a gate electrode coupled to said drain electrode of said first p-channel MOS transistor, wherein said supply potential is greater than said magnitude of said second potential signal.
Claim 8
Dependent Claim
38 words
A memory system in accordance with claim 1, wherein said sense signals include sense voltages developed by directing a sense current through said programmable resistance elements and said reference signals include reference voltages derived from a reference current.
Claim 9
Dependent Claim
58 words
A memory system in accordance with claim 7, further comprising: a first comparison circuit input line coupled to said selected one of said column lines, said sense current flowing through said first comparison circuit input line and through said selected one of said programmable resistance elements; and a second comparison circuit input line for conducting said reference current.
Claim 10
Dependent Claim
33 words
A memory system in accordance with claim 8, wherein said comparison circuit comprises: an amplifier circuit having first and second sense nodes respectively coupled to said first and second comparison input lines, respectively.
Claim 11
Dependent Claim
131 words
A memory system in accordance with claim 7, wherein said sense voltage and said reference voltage are generated on said first and second comparison circuit input lines, respectively, and when said sense voltage is greater than said reference voltage, said amplifier circuit drives said first sense node to a voltage higher than said sense voltage and drives said second sense node to a voltage less than said reference voltage, and when said sense voltage is less than said reference voltage, said amplifier circuit drives said first sense node to a voltage less than said sense voltage and drives said second sense node to a voltage higher than said reference voltage, said voltages on said first and second sense nodes are supplied to first and second output nodes of said amplifier, respectively.
Claim 12
Dependent Claim
55 words
A memory system in accordance with claim 9, further comprising: an isolation circuit coupled to said first and second comparison circuit input lines, wherein, in response to a control signal, said isolation circuit is rendered conductive to thereby connect said first and second sense nodes to said first and second comparison circuit input lines, respectively.
Claim 13
Dependent Claim
132 words
A memory system in accordance with claim 11, wherein said isolation circuit comprises: a first switching element having a first terminal coupled to said first comparison circuit input line, a second terminal coupled to said first sense node, and a control terminal receiving said control signal; and a second switching element having a first terminal coupled to said second comparison circuit input line, a second terminal coupled to said second sense node, and a control terminal receiving said control signal, wherein, upon application of said control signal to said control terminals of said first and second switching elements, said first and second switching elements are rendered conductive to connect said first sense node to said first comparison circuit input line and said second sense node to said second comparisons circuit input line.
Claim 14
Dependent Claim
16 words
A memory system in accordance with 9, wherein said amplifier circuit includes a cross-coupled latch circuit.
Claim 15
Dependent Claim
16 words
A memory system in accordance with 9, wherein said amplifier circuit includes a cross-coupled latch circuit.
Claim 16
Dependent Claim
17 words
A memory system in accordance with claim 13, wherein said cross-coupled latch circuit includes a flip-flop circuit.
Claim 17
Dependent Claim
45 words
A memory system in accordance with claim 9, further comprising: a precharge circuit coupled between said first and second sense nodes of said amplifier circuit, wherein upon application of a precharge signal to said precharge circuit, said first and second sense nodes are shorted together.
Claim 18
Dependent Claim
59 words
A memory system in accordance with claim 1, further comprising a write circuit coupled to said array of programmable resistance elements, said write circuit coupled to supply one of a first potential and a second potential to said array, said first potential and second potentials programming a selected programmable resistance element to said first and second resistance states, respectively.
Claim 19
Dependent Claim
140 words
A memory system in accordance with claim 1, wherein said programmable resistance elements are arranged in a plurality of columns and rows in said array, said memory system further comprising: a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in said columns; a plurality of row lines respectively coupled to pluralities of programmable resistance elements arranged in said rows; a column decoder circuit coupled to select one of said column lines at a time; a row decoder circuit coupled to select one of said row lines at a time; and a write circuit coupled to supply one of a first potential and a second potential to said array, said first potential and second potentials programming a programmable resistance element coupled to said selected row and column lines to said first and second resistance states, respectively.
Claim 20
Dependent Claim
40 words
A memory system in accordance with claim 16, wherein said first potential is supplied for a first duration to said selected programmable resistance element and said second potential is supplied for a second duration to said selected programmable resistance element.
Claim 21
Dependent Claim
142 words
A memory system in accordance with claim 18, wherein said write circuit further comprises: a first switching element having a first terminal for receiving said first potential, a second terminal coupled to an access node, and a control terminal for receiving a first pulse of said first duration; a second switching element having a first terminal for receiving said second potential, a second terminal coupled to said access node, and a control terminal for receiving a second pulse of said second duration, wherein said access node is connected to said array of programmable resistance elements, and said write circuit selectively applies said first and second pulses to said control terminals of said first and second switching elements, respectively, in order to selectively supply said first and second potentials having said first and second durations, respectively, to said array of programmable resistance elements.
Claim 22
Dependent Claim
33 words
A memory system in accordance with claim 19, wherein said write circuit further comprises: a first delay circuit for generating said first pulse; and a second delay circuit for generating said second pulse.
Claim 23
Dependent Claim
105 words
A memory system in accordance with claim 19, wherein said write circuit further comprises: a first driver circuit having an input node for receiving a first input pulse and an output node for supplying said first pulse to said control terminal of said first switching element, said first pulse having a voltage amplitude greater than said first input pulse; and a second driver circuit having an input node for receiving a second input pulse and an output node for supplying said second pulse to said control terminal of said second switching element, said second pulse having a voltage amplitude greater than said second input pulse.
Claim 24
Dependent Claim
153 words
A memory system in accordance with claim 21, wherein said first driver circuit includes: a n-channel MOS transistor having a source electrode for connection to a ground potential, a gate electrode for receiving an inverted first input signal, and a drain electrode connected to said output node of said first driver circuit; a first p-channel MOS transistor having a drain electrode coupled to said gate electrode of said n-channel transistor, a source electrode coupled to a supply potential, and a gate electrode coupled to said output node of said first driver circuit; and a second p-channel MOS transistor having a drain electrode coupled to a drain electrode of said n-channel MOS transistor, a source electrode coupled to said supply potential, and a gate electrode coupled to said drain electrode of said first p-channel MOS transistor, wherein a magnitude of said supply potential is greater than said voltage amplitude of said first input pulse.
Claim 25
Dependent Claim
18 words
A memory system in accordance with claim 19, wherein said first and second switching elements include MOS transistors.
Claim 26
Dependent Claim
22 words
A memory system in accordance with claim 1, wherein each of said programmable resistance elements in said array includes a chalcogenide material.
Claim 27
Dependent Claim
19 words
A memory system in accordance with claim 1, wherein each of said programmable resistance elements includes a programmable resistor.
Claim 28
Dependent Claim
63 words
A memory system in accordance with claim 25, wherein each of said programmable resistors has a first terminal and a second terminal, said first terminal is coupled to one of said column lines, each said programmable resistance elements further comprising: a potential barrier device, said potential barrier device coupled between said second terminal of said programmable resistor and one of said row lines.
Claim 29
Dependent Claim
16 words
A memory system in accordance with claim 26, wherein said potential barrier device includes a transistor.
Claim 30
Dependent Claim
16 words
A memory system in accordance with claim 26, wherein said potential barrier device includes a diode.
Claim 31
Dependent Claim
57 words
A memory system in accordance with claim 26, further comprising: a plurality of biasing circuits respectively coupled to each of said row lines, whereby, when said row lines are in a nonselected state, said plurality of biasing circuits supply a voltage to said nonselected word lines to reverse bias said potential barrier devices to a non-conductive condition.
Claim 32
Dependent Claim
32 words
A memory system in accordance with claim 8, further comprising a fixed resistance element coupled to said second comparison circuit input line, wherein said reference current flows through said fixed resistance element.
Claim 33
Dependent Claim
61 words
A memory system in accordance with claim 8, further comprising: a first shunt protection circuit coupled to said first comparison circuit input line; and a second shunt protection circuit coupled to said second comparison circuit input line, said first and second shunt protection circuits limiting said sense and reference currents flowing through said first and second comparison circuit inputs lines, respectively.
Claim 34
Dependent Claim
20 words
A memory system in accordance with claim 31, wherein said first and second shunt protection circuits each include a diode.
Claim 35
Dependent Claim
20 words
A memory system in accordance with claim 31, wherein said first and second shunt protection circuits each include a resistor.
Claim 36
Dependent Claim
26 words
A memory system in accordance with claim 31, wherein said first and second shunt protection circuits each include a diode connected in series with a resistor.
Claim 37
Dependent Claim
184 words
A semiconductor memory device comprising: a semiconductor substrate; a matrix array of memory cells arranged in plural rows and columns on said substrate, each memory cell including a resistor programmable to one of a first resistance state and a second resistance state; a plurality of column lines respectively coupled to the plural columns of memory cells; a plurality of row lines respectively coupled to the plural rows of memory cells; a column decoder circuit connected to select one of said column lines; a row decoder circuit connected to select one of said row lines; a column output line coupled to each of said column lines; a reference line coupled to a fixed resistance element; and a comparator circuit coupled to said column output line and said reference line, said comparator circuit comparing a sense current flowing through said column output line and a selected programmable resistor coupled to said selected one of said row lines and a reference current flowing through said reference line and said fixed resistance element to thereby output a signal indicative of a resistance state of said programmable resistance element.
Claim 38
Dependent Claim
184 words
A semiconductor memory device comprising: a semiconductor substrate; a matrix array of memory cells arranged in plural rows and columns on said substrate, each memory cell including a resistor programmable to one of a first resistance state and a second resistance state; a plurality of column lines respectively coupled to the plural columns of memory cells; a plurality of row lines respectively coupled to the plural rows of memory cells; a column decoder circuit connected to select one of said column lines; a row decoder circuit connected to select one of said row lines; a column output line coupled to each of said column lines; a reference line coupled to a fixed resistance element; and a comparator circuit coupled to said column output line and said reference line, said comparator circuit comparing a sense current flowing through said column output line and a selected programmable resistor coupled to said selected one of said row lines and a reference current flowing through said reference line and said fixed resistance element to thereby output a signal indicative of a resistance state of said programmable resistance element.
Claim 39
Dependent Claim
19 words
A semiconductor memory device in accordance with claim 35, wherein each of said programmable resistors includes a chalcogenide material.
Claim 40
Dependent Claim
186 words
A semiconductor memory device comprising: a semiconductor substrate; an array of programmable resistance elements formed on said substrate, each including a resistor programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of rows and columns; a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns; a plurality of row lines respectively coupled to pluralities of programmable resistance elements arranged in each of said rows; a column decoder circuit connected to select one of said column lines; a row decoder circuit connected to select one of said row lines; a column output line coupled to each of said column lines; a write circuit coupled to said column output line to supply one of a first write voltage and a second write voltage to one of said programmable resistors coupled to said selected column line and said selected row line, said first write voltage programming said programmable resistor to said first resistance state and said second write voltage programming said programmable resistor to said second resistance state.
Claim 41
Dependent Claim
186 words
A semiconductor memory device comprising: a semiconductor substrate; an array of programmable resistance elements formed on said substrate, each including a resistor programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of rows and columns; a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns; a plurality of row lines respectively coupled to pluralities of programmable resistance elements arranged in each of said rows; a column decoder circuit connected to select one of said column lines; a row decoder circuit connected to select one of said row lines; a column output line coupled to each of said column lines; a write circuit coupled to said column output line to supply one of a first write voltage and a second write voltage to one of said programmable resistors coupled to said selected column line and said selected row line, said first write voltage programming said programmable resistor to said first resistance state and said second write voltage programming said programmable resistor to said second resistance state.
Claim 42
Dependent Claim
90 words
A semiconductor memory device comprising: an array of programmable resistance elements, each including a resistor programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of rows and columns; a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns; a column output line coupled to each of said column lines; and a shunt protection circuit coupled to limit a current flowing through said column output line and said column lines.
Claim 43
Dependent Claim
90 words
A semiconductor memory device comprising: an array of programmable resistance elements, each including a resistor programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of rows and columns; a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns; a column output line coupled to each of said column lines; and a shunt protection circuit coupled to limit a current flowing through said column output line and said column lines.
Claim 44
Dependent Claim
17 words
A semiconductor memory device in accordance with claim 38, wherein said shunt protection circuit includes a diode.
Claim 45
Dependent Claim
17 words
A semiconductor memory device in accordance with claim 38, wherein said shunt protection circuit includes a resistor.
Claim 46
Dependent Claim
23 words
A semiconductor memory device in accordance with claim 38, wherein said shunt protection circuit includes a diode connected in series with a resistor.
Claim 47
Independent Claim
194 words
A method of operating a memory, said memory including an array of programmable resistance elements, each programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in pluralities of rows and columns; a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in said columns; a plurality of row lines respectively coupled to pluralities of programmable resistance elements arranged in said rows; a column decoder circuit connected to select one of said column lines; and a row decoder circuit connected to select one of said row lines, said method comprising the steps of: driving one of said plurality of column lines to a first potential in accordance with an output of said column decoder; driving one of said plurality of row lines to a second potential in accordance with an output of said row decoder; directing a sense current though a programmable resistance element coupled to said one of said plurality of column lines and said one of said plurality of row lines; and comparing said sense current with a reference current, to determine a programmed resistance of said programmable resistance element.
Claim 48
Independent Claim
194 words
A method of operating a memory, said memory including an array of programmable resistance elements, each programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in pluralities of rows and columns; a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in said columns; a plurality of row lines respectively coupled to pluralities of programmable resistance elements arranged in said rows; a column decoder circuit connected to select one of said column lines; and a row decoder circuit connected to select one of said row lines, said method comprising the steps of: driving one of said plurality of column lines to a first potential in accordance with an output of said column decoder; driving one of said plurality of row lines to a second potential in accordance with an output of said row decoder; directing a sense current though a programmable resistance element coupled to said one of said plurality of column lines and said one of said plurality of row lines; and comparing said sense current with a reference current, to determine a programmed resistance of said programmable resistance element.
Claim 49
Dependent Claim
139 words
A method of operating a memory in accordance with claim 42, wherein said memory further includes a comparator circuit having first and second nodes, a first comparator input line coupled to each of said plurality of column lines and said comparator circuit, and a second comparator input line coupled to a fixed resistance element and said comparator circuit, said comparing step further comprising the steps of: precharging said first and second nodes of said comparator circuit to a third potential; connecting said first and second comparator input lines to said first and second comparator nodes, respectively; driving said first comparison input line and said first comparison input node to a sense voltage proportional to said sense current; and driving said second comparison input line and said second comparison input node to a reference voltage proportion to said reference current.
Claim 50
Dependent Claim
118 words
A method in accordance with claim 43, further comprising the steps of: electrically isolating said first comparison input line from said first comparison node and said second comparison input line from said second comparison node; driving said isolated first comparison node to a fourth voltage higher than said sense voltage and driving said isolated second comparison node to a fifth voltage less than said reference voltage when said sense voltage is higher than said reference voltage; driving said isolated first comparison node to said fifth voltage, and driving said isolated second comparison node to said fourth voltage when said sense voltage is less than said fifth voltage; and outputting voltages appearing on said first and second comparison nodes.
Claim 51
Dependent Claim
26 words
A method in accordance with claim 42, further comprising the step of limiting a potential appearing on said column lines to not exceed a predetermined value.
Claim 52
Independent Claim
92 words
A method of operating a memory, said memory including an array of programmable resistance elements, each programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of columns; a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns, said method comprising the steps of: supplying a current to one of said column lines; and coupling a shunt circuit to said column lines to limit said current to not exceed a predetermined magnitude.
Claim 53
Independent Claim
92 words
A method of operating a memory, said memory including an array of programmable resistance elements, each programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of columns; a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns, said method comprising the steps of: supplying a current to one of said column lines; and coupling a shunt circuit to said column lines to limit said current to not exceed a predetermined magnitude.
Claim 54
Dependent Claim
71 words
A memory system comprising: an array of programmable resistance elements, each of which comprising a chalcogenide material and being programmable to one of a first resistance state and a second resistance state; and a comparison circuit coupled to said array of programmable resistance elements, said comparison circuit adapted to compare sense signals developed by said programmable resistance elements and reference signals, and to generate readout signals in response to said comparisons.
Claim 55
Dependent Claim
71 words
A memory system comprising: an array of programmable resistance elements, each of which comprising a chalcogenide material and being programmable to one of a first resistance state and a second resistance state; and a comparison circuit coupled to said array of programmable resistance elements, said comparison circuit adapted to compare sense signals developed by said programmable resistance elements and reference signals, and to generate readout signals in response to said comparisons.
Claim 56
Dependent Claim
114 words
A memory system in accordance with claim 47, wherein said programmable resistance elements are arranged in a plurality of columns and rows in said array, said memory system further comprising: a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in said columns; a plurality of row lines respectively coupled to pluralities of programmable resistance elements arranged in said rows; a column decoder circuit coupled to select one of said column lines; and a row decoder circuit coupled to select one of said row lines, thereby selecting one of said programmable resistance elements coupled to said selected column line and said selected row line for coupling with said comparison circuit.
Claim 57
Dependent Claim
38 words
A memory system in accordance with claim 48, wherein said column decoder has a plurality of outputs respectively corresponding to said plurality of column lines, one of said plurality of outputs operable to select said selected column line.
Claim 58
Dependent Claim
97 words
A memory system in accordance with claim 49, wherein said column decoder circuit further comprises: a plurality of driver circuits respectively coupled to said plurality of outputs of said column decoder, one of said plurality of driver circuits coupled to said one output and generating a first potential signal operable to select said selected column line, remaining ones of said plurality of driver circuits receiving a second potential signal and supplying, in response thereto, a third potential signal to said remaining outputs of said column decoder, thereby deselecting said column lines other than said selected column line.
Claim 59
Dependent Claim
26 words
A memory system in accordance with claim 50, wherein a magnitude of said first potential signal being greater than a magnitude of said second potential signal.
Claim 60
Dependent Claim
20 words
A memory system in accordance with claim 50, wherein each of said plurality of driver circuits includes an inverter circuit.
Claim 61
Dependent Claim
147 words
A memory system in accordance with claim 50, wherein each of said plurality of driver circuits respectively includes: a n-channel MOS transistor having a source electrode for connection to a ground potential, a gate electrode for receiving an input signal, and a drain electrode connected to said output node of said first driver circuit; a first p-channel MOS transistor having a drain electrode coupled to said gate electrode of said n-channel transistor, a source electrode coupled to a supply potential, and a gate electrode coupled to said driver circuit output; and a second p-channel MOS transistor having a drain electrode coupled to a drain electrode of said n-channel MOS transistor, a source electrode coupled to said supply potential, and a gate electrode coupled to said drain electrode of said first p-channel MOS transistor, wherein said supply potential is greater than said magnitude of said second potential signal.
Claim 62
Dependent Claim
40 words
A memory system in accordance with claim 48, wherein said sense signals include a sense voltage developed by supplying a sense current through said programmable resistance elements and said reference signals include a reference voltage derived from a reference current.
Claim 63
Dependent Claim
58 words
A memory system in accordance with claim 54, further comprising: a first comparison circuit input line coupled to said selected one of said column lines, said sense current flowing through said first comparison circuit input line and through said selected one of said programmable resistance element; and a second comparison circuit input line for conducting said reference current.
Claim 64
Dependent Claim
33 words
A memory system in accordance with claim 55, wherein said comparison circuit comprises: an amplifier circuit having first and second sense nodes respectively coupled to said first and second comparison input lines, respectively.
Claim 65
Dependent Claim
131 words
A memory system in accordance with claim 56, wherein said reference voltage and said sense voltage are generated on said first and second comparison circuit input lines, respectively, and when said sense voltage is greater than said reference voltage, said amplifier circuit drives said first sense node to a voltage higher than said sense voltage and drives said second sense node to a voltage less than said reference voltage, and when said sense voltage is less than said reference voltage, said amplifier circuit drives said first sense node to a voltage less than said sense voltage and drives said second sense node to a voltage higher than said reference voltage, said voltages on said first and second sense nodes are supplied to first and second output nodes of said amplifier, respectively.
Claim 66
Dependent Claim
55 words
A memory system in accordance with claim 56, further comprising: an isolation circuit coupled to said first and second comparison circuit input lines, wherein, in response to a control signal, said isolation circuit is rendered conductive to thereby connect said first and second sense nodes to said first and second comparison circuit input lines, respectively.
Claim 67
Dependent Claim
132 words
A memory system in accordance with claim 58, wherein said isolation circuit comprises: a first switching element having a first terminal coupled to said first comparison circuit input line, a second terminal coupled to said first sense node, and a control terminal receiving said control signal; and a second switching element having a first terminal coupled to said second comparison circuit input line, a second terminal coupled to said second sense node, and a control terminal receiving said control signal, wherein, upon application of said control signal to said control terminals of said first and second switching elements, said first and second switching elements are rendered conductive to connect said first sense node to said first comparison circuit input line and said second sense node to said second comparisons circuit input line.
Claim 68
Dependent Claim
16 words
A memory system in accordance with 56, wherein said amplifier circuit includes a cross-coupled latch circuit.
Claim 69
Dependent Claim
16 words
A memory system in accordance with 56, wherein said amplifier circuit includes a cross-coupled latch circuit.
Claim 70
Dependent Claim
17 words
A memory system in accordance with claim 60, wherein said dross-coupled latch circuit includes a flip-flop circuit.
Claim 71
Dependent Claim
45 words
A memory system in accordance with claim 56, further comprising: a precharge circuit coupled between said first and second sense nodes of said amplifier circuit, wherein upon application of a precharge signal to said precharge circuit, said first and second sense nodes are shorted together.
Claim 72
Dependent Claim
45 words
A memory system in accordance with claim 47, further comprising a write circuit coupled to supply one of a first write signal and a second write signal to said array for programming a selected programmable resistance element to said first and second resistance states, respectively.
Claim 73
Dependent Claim
133 words
A memory system in accordance with claim 47, wherein said programmable resistance elements are arranged in a plurality of columns and rows in said array, said memory system further comprising: a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in said columns; a plurality of row lines respectively coupled to pluralities of programmable resistance elements arranged in said rows; a column decoder circuit connected to select one of said column lines at a time; a row decoder circuit connected to select one of said row lines at a time; and a write circuit coupled to supply one of first and second write signals to program a selected programmable resistance element coupled to said selected row and column lines to either of said first and second resistance states, respectively.
Claim 74
Dependent Claim
40 words
A memory system in accordance with claim 63, wherein said first potential is supplied to said selected programmable resistance element for a first duration, and said second potential is supplied for a second duration to said selected programmable resistance element.
Claim 75
Dependent Claim
140 words
A memory system in accordance with claim 65, wherein said write circuit further comprises: a first switching element having a first terminal for receiving said first potential, a second terminal coupled to an access node, and a control terminal for receiving a first pulse of said first duration; a second switching element having a first terminal for receiving said second potential, a second terminal coupled to said access node, and a control terminal for receiving a second pulse of said second duration, wherein said access node is connected to said array of programmable resistance elements, and said write circuit selectively applying said first and second pulses to said control terminals of said first and second switching elements, respectively, to selectively supply said first and second potentials having said first and second durations, respectively, to said array of programmable resistance elements.
Claim 76
Dependent Claim
33 words
A memory system in accordance with claim 66, wherein said write circuit further comprises: a first delay circuit for generating said first pulse; and a second delay circuit for generating said second pulse.
Claim 77
Dependent Claim
105 words
A memory system in accordance with claim 66, wherein said write circuit further comprises: a first driver circuit having an input node for receiving a first input pulse and an output node for supplying said first pulse to said control terminal of said first switching element, said first pulse having a voltage amplitude greater than said first input pulse; and a second driver circuit having an input node for receiving a second input pulse and an output node for supplying said second pulse to said control terminal of said second switching element, said second pulse having a voltage amplitude greater than said second input pulse.
Claim 78
Dependent Claim
153 words
A memory system in accordance with claim 68, wherein said first driver circuit includes: a n-channel MOS transistor having a source electrode for connection to a ground potential, a gate electrode for receiving an inverted first input signal, and a drain electrode connected to said output node of said first driver circuit; a first p-channel MOS transistor having a drain electrode coupled to said gate electrode of said n-channel transistor, a source electrode coupled to a supply potential, and a gate electrode coupled to said output node of said first driver circuit; and a second p-channel MOS transistor having a drain electrode coupled to a drain electrode of said n-channel MOS transistor, a source electrode coupled to said supply potential, and a gate electrode coupled to said drain electrode of said first p-channel MOS transistor, wherein a magnitude of said supply potential is greater than said voltage amplitude of said first input pulse.
Claim 79
Dependent Claim
18 words
A memory system in accordance with claim 66, wherein said first and second switching elements include MOS transistors.
Claim 80
Dependent Claim
19 words
A memory system in accordance with claim 48, wherein each of said programmable resistance elements includes a programmable resistor.
Claim 81
Dependent Claim
63 words
A memory system in accordance with claim 71, wherein each of said programmable resistors has a first terminal and a second terminal, said first terminal is coupled to one of said column lines, each said programmable resistance elements further comprising: a potential barrier device, said potential barrier device coupled between said second terminal of said programmable resistor and one of said row lines.
Claim 82
Dependent Claim
16 words
A memory system in accordance with claim 72, wherein said potential barrier device includes a transistor.
Claim 83
Dependent Claim
16 words
A memory system in accordance with claim 72, wherein said potential barrier device includes a diode.
Claim 84
Dependent Claim
57 words
A memory system in accordance with claim 72, further comprising: a plurality of biasing circuits respectively coupled to each of said row lines, whereby, when said row lines are in a nonselected state, said plurality of biasing circuits supply a voltage to said nonselected word lines to reverse bias said potential barrier devices to a non-conductive condition.
Claim 85
Dependent Claim
32 words
A memory system in accordance with claim 55, further comprising a fixed resistance element coupled to said second comparison circuit input line, wherein said reference current flows through said fixed resistance element.
Claim 86
Dependent Claim
61 words
A memory system in accordance with claim 55, further comprising: a first shunt protection circuit coupled to said first comparison circuit input line; and a second shunt protection circuit coupled to said second comparison circuit input line, said first and second shunt protection circuits limiting said sense and reference currents flowing through said first and second comparison circuit inputs lines, respectively.
Claim 87
Dependent Claim
20 words
A memory system in accordance with claim 77, wherein said first and second shunt protection circuits each include a diode.
Claim 88
Dependent Claim
20 words
A memory system in accordance with claim 77, wherein said first and second shunt protection circuits each include a resistor.
Claim 89
Dependent Claim
26 words
A memory system in accordance with claim 77, wherein said first and second shunt protection circuits each include a diode connected in series with a resistor.
Claim 90
Dependent Claim
92 words
A semiconductor memory device comprising: an array of programmable resistance elements, each including a resistor comprising chalcogenide material and being programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of rows and columns; a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns; a column output line coupled each of said column lines; and a shunt protection circuit limiting a current flowing through said column output line and said column lines.
Claim 91
Dependent Claim
92 words
A semiconductor memory device comprising: an array of programmable resistance elements, each including a resistor comprising chalcogenide material and being programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of rows and columns; a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns; a column output line coupled each of said column lines; and a shunt protection circuit limiting a current flowing through said column output line and said column lines.
Claim 92
Dependent Claim
17 words
A semiconductor memory device in accordance with claim 81, wherein said shunt protection circuit includes a diode.
Claim 93
Dependent Claim
17 words
A semiconductor memory device in accordance with claim 81, wherein said shunt protection circuit includes a resistor.
Claim 94
Dependent Claim
23 words
A semiconductor memory device in accordance with claim 81, wherein said shunt protection circuit includes a diode connected in series with a resistor.
Claim 95
Dependent Claim
48 words
A memory system in accordance with one of claims 6, 22 or 53, wherein said n-channel transistor is a first n-channel transistor, said memory system further comprising: a second n-channel transistor connected between said drain of said first p-channel transistor and said gate of said first n-channel transistor.
Claim 96
Dependent Claim
58 words
A memory system in accordance with claim 8 or 55, further comprising: a first shunt protection circuit coupled to said first comparison circuit input line; and a second shunt protection circuit coupled to said second comparison circuit input line, said first and second shunt protection circuits limiting voltages appearing on said first and second comparison circuit input lines.
Claim 97
Dependent Claim
89 words
A semiconductor memory device comprising: an array of programmable resistance elements, each including a resistor programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of rows and columns; a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns; a column output line coupled to each of said column lines; and a shunt protection circuit coupled to limit voltages appearing on said column output line and said column lines.
Claim 98
Dependent Claim
89 words
A semiconductor memory device comprising: an array of programmable resistance elements, each including a resistor programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of rows and columns; a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns; a column output line coupled to each of said column lines; and a shunt protection circuit coupled to limit voltages appearing on said column output line and said column lines.
Claim 99
Dependent Claim
17 words
A semiconductor memory device in accordance with claim 87, wherein said shunt protection circuit includes a diode.
Claim 100
Dependent Claim
17 words
A semiconductor memory device in accordance with claim 87, wherein said shunt protection circuit includes a resistor.
Claim 101
Dependent Claim
23 words
A semiconductor memory device in accordance with claim 87, wherein said shunt protection circuit includes a diode connected in series with a resistor.
Claim 102
Dependent Claim
18 words
A semiconductor memory device in accordance with claim 87, wherein each said programmable resistors include a chalcogenide material.
Claim 103
Independent Claim
99 words
A method of operating a memory, said memory including an array of programmable resistance elements, each programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of columns; a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns, said method comprising the steps of: supplying a current to one of said column lines; and coupling a shunt circuit to said column lines to limit a voltage on said one of said column lines to not exceed a predetermined magnitude.
Claim 104
Independent Claim
99 words
A method of operating a memory, said memory including an array of programmable resistance elements, each programmable to one of a first resistance value and a second resistance value, said programmable resistance elements arranged in a plurality of columns; a plurality of column lines respectively coupled to pluralities of programmable resistance elements arranged in each of said columns, said method comprising the steps of: supplying a current to one of said column lines; and coupling a shunt circuit to said column lines to limit a voltage on said one of said column lines to not exceed a predetermined magnitude.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-15 | 2002-09-14 | 2003-03-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-15 | 2006-09-14 | 2007-03-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-15 | 2010-09-14 | 2011-03-16 | $7700.00 | Window Closed / Lapsed |