US5898328A
Expired / Lapsed
US
⏱️ 0.0 years remaining
PLL circuit having a switched charge pump for charging a loop filter up or down and signal processing apparatus using the same
Assignee: Sony Corp
•
Filing: 1997-04-10
•
Granted: 1999-04-27
•
Expires: 2017-04-10
Abstract
Abstract The invention provides a PLL circuit which can form a phase difference between input and output signals with a high degree of accuracy without employing a current source for a very weak current and eliminates dependency of the phase difference upon the input signal frequency. In the PLL circuit, phase difference forming current is added within a term of a fixed period to a selected one of charge-up current and charge-down current, selected by a phase comparison circuit, of a charge pump circuit, which charges up or charges down a loop filter under the control of an output signal of a phase comparison circuit, to form a phase difference between input and output signals of the PLL circuit which are to be compared in phase by the phase comparison circuit. The magnitude of the phase difference depends upon and is controlled by a term within which the phase difference forming current.
Inventors
- 👤 Norio Shoji
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 09:15
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; H03L7/0891
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
150 words
A PLL circuit, comprising: a phase comparator for comparing phases of an input signal and a comparison signal with each other; a first control signal generation circuit for receiving the input signal to generate a first control signal; a charge pump circuit including a first current source and a second current source which are controlled by an output signal of said comparator and a third current source which is controlled by a second control signal; a voltage controlled oscillation circuit having an oscillation frequency controlled by an output signal of said charge pump circuit; a first counter for counting an output signal of said voltage controlled oscillation circuit and applving a resulting count thereof as the comparison signal to said phase comparator; and a second counter for counting an output signal of said voltage controlled oscillation circuit in response to the first control signal to generate the second control signal.
Claim 2
Dependent Claim
150 words
A PLL circuit, comprising: a phase comparator for comparing phases of an input signal and a comparison signal with each other; a first control signal generation circuit for receiving the input signal to generate a first control signal; a charge pump circuit including a first current source and a second current source which are controlled by an output signal of said comparator and a third current source which is controlled by a second control signal; a voltage controlled oscillation circuit having an oscillation frequency controlled by an output signal of said charge pump circuit; a first counter for counting an output signal of said voltage controlled oscillation circuit and applving a resulting count thereof as the comparison signal to said phase comparator; and a second counter for counting an output signal of said voltage controlled oscillation circuit in response to the first control signal to generate the second control signal.
Claim 3
Dependent Claim
21 words
The PLL circuit according to claim 1, wherein said first and third current sources are connected in parallel to each other.
Claim 4
Dependent Claim
28 words
The PLL circuit according to claim 2, wherein a current value of said third current source is set lower than a current value of said first current source.
Claim 5
Dependent Claim
28 words
The PLL circuit according to claim 3, wherein a conducting period of said third current source is set longer than a conducting period of said first current source.
Claim 6
Dependent Claim
20 words
The PLL circuit according to claim 1, wherein said first control signal generation circuit includes a synchronizing signal generation circuit.
Claim 7
Dependent Claim
66 words
The PLL circuit according to claim 1, wherein said charge pump further includes switching means for connecting said third current source with either one of said first current source and second current source such that a current from said third current source is added to a current from either one of said first current source and second current source within a term of a fixed period.
Claim 8
Dependent Claim
43 words
The PLL circuit according to claim 6, wherein said switching means is controlled by said second control signal from said second counter which counts the output signal of said PLL circuit up to a number corresponding to a phase difference to be formed.
Claim 9
Dependent Claim
25 words
The PLL circuit according to claim 6, wherein said switching means is cleared by a synchronizing signal from the input signal to said PLL circuit.
Claim 10
Dependent Claim
222 words
A signal processing apparatus which converts an analog signal having a synchronizing signal generated after each fixed period into a digital signal by means of an analog to digital converter, comprising: a synchronizing signal detection circuit for detecting a synchronizing signal from the analog signal; and a PLL circuit for receiving the synchronizing signal and sending out an output signal thereof as an operation control signal to said digital to analog converter, said PLL circuit including, a phase comparator for comparing phases of an input signal and a comparison signal with each other, a first control signal generation circuit for receiving the input signal to generate a first control signal, a charge pump circuit including a first current source and a second current source which are controlled by an output signal of said comparator and a third current source which is controlled by a second control signal, a voltage controlled oscillation circuit having an oscillation frequency controlled by an output signal of said charge pump circuit, a first counter for counting an output signal of said voltage controlled oscillation circuit and applying a resulting count thereof as the comparison signal to said phase comparator, and a second counter for counting an output signal of said voltage controlled oscillation circuit in response to the first control signal to generate the second control signal.
Claim 11
Dependent Claim
222 words
A signal processing apparatus which converts an analog signal having a synchronizing signal generated after each fixed period into a digital signal by means of an analog to digital converter, comprising: a synchronizing signal detection circuit for detecting a synchronizing signal from the analog signal; and a PLL circuit for receiving the synchronizing signal and sending out an output signal thereof as an operation control signal to said digital to analog converter, said PLL circuit including, a phase comparator for comparing phases of an input signal and a comparison signal with each other, a first control signal generation circuit for receiving the input signal to generate a first control signal, a charge pump circuit including a first current source and a second current source which are controlled by an output signal of said comparator and a third current source which is controlled by a second control signal, a voltage controlled oscillation circuit having an oscillation frequency controlled by an output signal of said charge pump circuit, a first counter for counting an output signal of said voltage controlled oscillation circuit and applying a resulting count thereof as the comparison signal to said phase comparator, and a second counter for counting an output signal of said voltage controlled oscillation circuit in response to the first control signal to generate the second control signal.
References Cited (Backward Citations)
US4885554A
Cited
US5036216A
Cited
US5144156A
Cited
US5208546A
Cited
US5663688A
Cited
US5475326A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-26 | 2002-10-26 | 2003-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-26 | 2006-10-26 | 2007-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-26 | 2010-10-26 | 2011-04-27 | $7700.00 | Window Closed / Lapsed |