US5901090A
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Method for erasing flash electrically erasable programmable read-only memory (EEPROM)
Assignee: Monterey Research LLC
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Filing: 1998-05-27
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Granted: 1999-05-04
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Expires: 2018-05-27
Abstract
Abstract A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate, and a power source for supplying a plurality of voltages to the cells. A controller controls the power source to apply at least one erase pulse to the cells. Then, at least one overerase correction or "soft programming" pulse is applied to the cells during which the source, drain and control gate voltages of the cells are such that the threshold voltages of overerased cells will be increased, but least erased cells will not be disturbed. The overerase correction pulses thereby tighten the threshold voltage distribution. A source to substrate bias voltage is applied for the duration of the overerase correction pulses which reduces the background leakage of the cells to a level at which the overerase correction operation can be effectively performed, even in applications with low supply voltages.
Inventors
- 👤 Sameer S. Haddad
- 👤 Wing H. Leung
- 👤 John Chen
- 👤 Ravi S. Sunkavalli
- 👤 Ravi P. Gutala
- 👤 Jonathan S. Su
- 👤 Colin S. Bill
- 👤 Vei-Han Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 08:58
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3404; G11C16/3409; G11C16/10; G11C16/14; G11C16/16
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
96 words
A method for erasing a flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) which includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate, comprising the steps of: (a) applying at least one erase pulse to a plurality of the cells; and (b) applying at least one overerase correction pulse to said plurality of the cells during which source, drain and control gate voltages of the cells are such that threshold voltages of overerased cells will be increased, but threshold voltages of least erased cells will not be increased.
Claim 2
Independent Claim
96 words
A method for erasing a flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) which includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate, comprising the steps of: (a) applying at least one erase pulse to a plurality of the cells; and (b) applying at least one overerase correction pulse to said plurality of the cells during which source, drain and control gate voltages of the cells are such that threshold voltages of overerased cells will be increased, but threshold voltages of least erased cells will not be increased.
Claim 3
Dependent Claim
24 words
A method as in claim 1, in which the control gate voltage is approximately equal to a threshold voltage of a least erased cell.
Claim 4
Dependent Claim
30 words
A method as in claim 1, in which: the cells are arranged in a plurality of sectors; and the method comprises performing steps (a) and (b) on the sectors sequentially.
Claim 5
Dependent Claim
39 words
A method as in claim 1, in which: the memory further comprises a substrate; and step (b) further comprises applying a voltage to the substrate which is lower than the source voltage and reduces leakage current in the cells.
Claim 6
Dependent Claim
22 words
A method as in claim 4, in which step (b) comprises grounding the substrate and applying a positive voltage to the source.
Claim 7
Dependent Claim
22 words
A method as in claim 4, in which step (b) comprises grounding the source and applying a negative voltage to the substrate.
Claim 8
Dependent Claim
23 words
A method as in claim 4, in which step (b) comprises connecting electrical resistance between the sources of the cells and the substrate.
Claim 9
Dependent Claim
30 words
A method as in claim 4, in which: the cells are arranged in a plurality of sectors; and the method comprises performing steps (a) and (b) on the sectors sequentially.
Claim 10
Dependent Claim
32 words
A method as in claim 1, in which the control gate voltage is higher than the source voltage and the drain voltage is higher than the control gate voltage in step (b).
Claim 11
Dependent Claim
39 words
A method as in claim 9, in which: the memory further comprises a substrate; and step (b) further comprises applying a voltage to the substrate which is lower than the source voltage and reduces leakage current in the cells.
Claim 12
Dependent Claim
37 words
A method as in claim 1, in which: step (a) comprises performing a complete erase and Automatic Program Disturb (APD) procedure to said plurality of the cells; and step (b) is performed after completion of step (a).
Claim 13
Dependent Claim
105 words
A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM), comprising: a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate; a power source for supplying a plurality of voltages; and a controller for controlling the power source to apply at least one erase pulse to a plurality of the cells; and subsequently to apply at least one overerase correction pulse to said plurality of the cells during which source, drain and control gate voltages of the cells are such that threshold voltages of overerased cells will be increased, but threshold voltages of least erased cells will not be increased.
Claim 14
Dependent Claim
105 words
A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM), comprising: a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate; a power source for supplying a plurality of voltages; and a controller for controlling the power source to apply at least one erase pulse to a plurality of the cells; and subsequently to apply at least one overerase correction pulse to said plurality of the cells during which source, drain and control gate voltages of the cells are such that threshold voltages of overerased cells will be increased, but threshold voltages of least erased cells will not be increased.
Claim 15
Dependent Claim
38 words
A memory as in claim 11, in which the controller controls the power source to apply a voltage to the control gates of the cells which is approximately equal to a threshold voltage of a least erased cell.
Claim 16
Dependent Claim
36 words
A memory as in claim 12, in which: the cells are arranged in a plurality of sectors; and the controller controls the power source to apply the erase and overerase correction pulses to the sectors sequentially.
Claim 17
Dependent Claim
53 words
A memory as in claim 12, in which: the memory further comprises a substrate; and the controller controls the power source to apply a voltage to the substrate for the duration of said at least one overerase correction pulse which is lower than the source voltage and reduces leakage current in the cells.
Claim 18
Dependent Claim
26 words
A memory as in claim 15, in which the controller controls the power source to ground the substrate and apply a positive voltage to the source.
Claim 19
Dependent Claim
26 words
A memory as in claim 15, in which the controller controls the power source to ground the source and apply a negative voltage to the substrate.
Claim 20
Dependent Claim
36 words
A memory as in claim 15, in which controller causes an electrical resistance to be connected between the sources of the cells and the substrate for the duration of said at least one overerase correction pulse.
Claim 21
Dependent Claim
36 words
A memory as in claim 15, in which: the cells are arranged in a plurality of sectors; and the controller controls the power source to apply the erase and overerase correction pulses to the sectors sequentially.
Claim 22
Dependent Claim
29 words
A memory as in claim 12, in which the control gate voltage is higher than the source voltage and the drain voltage is higher than the control gate voltage.
Claim 23
Dependent Claim
53 words
A memory as in claim 20, in which: the memory further comprises a substrate; and the controller controls the power source to apply a voltage to the substrate for the duration of said at least one overerase correction pulse which is lower than the source voltage and reduces leakage current in the cells.
Claim 24
Dependent Claim
48 words
A memory as in claim 12, in which the controller controls the power source to perform a complete erase and Automatic Program Disturb (APD) procedure to said plurality of the cells, and subsequently to apply said at least one overerase correction pulse to said plurality of the cells.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-03 | 2002-11-02 | 2003-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-03 | 2006-11-02 | 2007-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-03 | 2010-11-02 | 2011-05-04 | $7700.00 | Window Closed / Lapsed |