US5905678A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Control circuit of an output buffer
Assignee: Micron Technology Inc
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Filing: 1997-09-19
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Granted: 1999-05-18
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Expires: 2017-09-19
Abstract
Abstract The invention relates to a control circuit for an output buffer, of the type which comprises a first input terminal receiving a first enable signal and a second input terminal receiving a second enable signal, as well as first and second output terminals to generate first and second partial enable signals to transfer discrete sets of data bits. The first and second input terminals are coupled to the first and second output terminals through a multiplexer. The control circuit includes a synchronization circuit for linking the partial enable signals operatively to a synchronization signal of the pulse type being synchronous with the loading of the output buffer. The synchronization circuit is connected between an output terminal of the multiplexer and the first and second output terminals of the control circuit.
Inventors
- 👤 Luigi Pascucci
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:53
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
135 words
A control circuit for an output buffer comprising: a first input terminal receiving a first enable signal and a second input terminal receiving a second enable signal; first and second output terminals to generate first and second partial enable signals to transfer discrete sets of data bits; a third input terminal receiving a multiplexer selection control signal; one of said first and second input terminals being selected by said multiplexer selection control signal and coupled to said first and second output terminals through a multiplexer; a synchronization circuit for linking the partial enable signals operatively to a synchronization signal of the pulse type being synchronous with the loading of the output buffer, said synchronization circuit being connected between an output terminal of said multiplexer and said first and second output terminals of said control circuit.
Claim 2
Dependent Claim
135 words
A control circuit for an output buffer comprising: a first input terminal receiving a first enable signal and a second input terminal receiving a second enable signal; first and second output terminals to generate first and second partial enable signals to transfer discrete sets of data bits; a third input terminal receiving a multiplexer selection control signal; one of said first and second input terminals being selected by said multiplexer selection control signal and coupled to said first and second output terminals through a multiplexer; a synchronization circuit for linking the partial enable signals operatively to a synchronization signal of the pulse type being synchronous with the loading of the output buffer, said synchronization circuit being connected between an output terminal of said multiplexer and said first and second output terminals of said control circuit.
Claim 3
Dependent Claim
39 words
The control circuit unit according to claim 1, wherein said synchronization circuit has a first input terminal receiving the synchronization signal and a second input terminal connected to the output terminal of said multiplexer for receiving a disable signal.
Claim 4
Dependent Claim
60 words
The control circuit unit according to claim 2, further comprising a delay circuit connected between a first and a second voltage reference and connected to the output terminal of said multiplexer and to the second input terminal of said synchronization circuit, said delay circuit having a control terminal receiving a reference signal and an output terminal supplying the disable signal.
Claim 5
Dependent Claim
40 words
The control circuit unit according to claim 3, wherein said delay circuit comprises an asymmetrical delay network having a significant delay from a first edge of an enable signal and immediate natural propagation at a second edge of said signal.
Claim 6
Dependent Claim
88 words
The control circuit unit according to claim 4, wherein said asymmetrical delay network is connected between a first and a second voltage reference and includes an input terminal for receiving a regulating signal, at least a charge control transistor and a delay capacitor connected in series with each other between the first and second voltage references wherein said charge control transistor includes a control terminal connected to the input terminal, and an output terminal supplying a controlled disable signal synchronized to a first edge of the enable signal.
Claim 7
Dependent Claim
63 words
The control circuit unit according to claim 5, wherein the controlled disable signal switches from the first edge of the enable signal with a delay which is proportional to a charge or discharge time of the delay capacitor and substantially independent from the first voltage reference, said signal also switching with no or trivial delay from a second edge of the enable signal.
Claim 8
Dependent Claim
45 words
The control circuit unit according to claim 5, wherein the delay capacitor is connected to the output terminal by way of a series of first and second logic gates, said second logic gate having an input terminal connected to the output terminal of the multiplexer.
Claim 9
Dependent Claim
44 words
The control circuit unit according to claim 5, further comprising first and second enable transistors connected between the charge control transistor and the first and second voltage references, respectively, and including a control terminal connected to the input terminal of the asymmetrical delay network.
Claim 10
Dependent Claim
53 words
The control circuit unit according to claim 2, wherein said synchronization circuit has an output terminal supplying a synchronized enable signal to respective first common input terminals of first and second logic circuits, said first and second logic circuits being connected to the first and the second output terminals of the control circuit.
Claim 11
Dependent Claim
26 words
The control circuit unit according to claim 9, wherein said first and second logic circuits further include second common input terminals for receiving an enable signal.
Claim 12
Dependent Claim
44 words
The control circuit unit according to claim 9, wherein the first and second logic circuits respectively comprise first and second logic gates connected in series with each other between the common input terminals and the first and second output terminals of the control circuit.
Claim 13
Dependent Claim
25 words
The control circuit unit according to claim 11, wherein said first logic gate of the logic circuit receives a control signal at an input terminal.
Claim 14
Dependent Claim
19 words
The control circuit unit according to claim 1, wherein said synchronization circuit comprises a flip-flop of the SET-RESET type.
Claim 15
Dependent Claim
32 words
The control circuit unit according to claim 1, further comprising a logic gate connected between the output terminal of the multiplexer and the first and second output terminals of the control circuit.
Claim 16
Independent Claim
107 words
A method for a synchronous loading of data into an output buffer comprising the steps of: providing a control circuit receiving first and second enable signals; providing a multiplexer circuit; providing a third input terminal for receiving a multiplexer selection control signal; selecting one of said first and second enable signals by said multiplexer circuit as selected by said multiplexer selection control signal; generating first and second partial enable signals to transfer data in discrete sets of bits; and providing a synchronization signal of the pulse type which is synchronous with the output buffer loading and generated by a synchronization circuit to control the partial enable signals.
Claim 17
Independent Claim
107 words
A method for a synchronous loading of data into an output buffer comprising the steps of: providing a control circuit receiving first and second enable signals; providing a multiplexer circuit; providing a third input terminal for receiving a multiplexer selection control signal; selecting one of said first and second enable signals by said multiplexer circuit as selected by said multiplexer selection control signal; generating first and second partial enable signals to transfer data in discrete sets of bits; and providing a synchronization signal of the pulse type which is synchronous with the output buffer loading and generated by a synchronization circuit to control the partial enable signals.
Claim 18
Dependent Claim
67 words
The synchronous data loading method according to claim 15, further comprising the step of providing a delay circuit connected to said synchronization circuit and an asymmetrical delay network which features an immediate reaction to the occurrence of a first data reading cycle and a delayed action with respect to a synchronization circuit disabling operation to thereby produce a filtering action with respect to pulses of noisy origin.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-17 | 2002-11-16 | 2003-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-17 | 2006-11-16 | 2007-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-17 | 2010-11-16 | 2011-05-18 | $7700.00 | Window Closed / Lapsed |