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US5923385A Expired / Lapsed US ⏱️ 0.0 years remaining

Processing system with single-buffered display capture

Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1996-10-11
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Granted: 1999-07-13
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Expires: 2016-10-11
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Abstract

Abstract A method and apparatus for single-buffered display capture which eliminates a "tearing" problem inherent in certain conventional video display techniques. A video signal including a sequence of frames each having an even field and an odd field is applied to a video capture circuit. First and second sets of lines each representing a different subset of all the lines in a given even or odd field are captured in the video capture circuit and displayed by a video display circuit. The video capture circuit captures the first set of lines in an even field of the video signal during a time period in which the video display circuit displays the second set of lines in the even field. The video capture circuit also captures the second set of lines in an odd field of the video signal during a time period in which the video display circuit displays the first set of lines in the odd field. The video capture circuit utilizes an odd-numbered decimation factor to determine the first and second sets of lines from among all lines in the even and odd fields.

Inventors

  • 👤 Christopher Mills
  • 👤 Thomas R. Ayers

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 23:05
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/64; H04N9/641

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 176 words
A method of processing a video signal in a processing system including a video capture circuit and a video display circuit, the video signal including a sequence of frames each having an even field and an odd field, each of the even field and the odd field including corresponding first and second sets of lines, each set of lines representing a predetermined subset of all lines in a given even or odd field, the method comprising the steps of selecting an odd-numbered decimation factor for use in the video capture circuit to determine the first and second sets of lines from all lines in the even and odd fields; capturing the determined first set of lines in the even field of the video signal during a time period in which the second set of lines in the even field are being displayed; and capturing the determined second set of lines in the odd field of the video signal during a time period in which the first set of lines in the odd field are being displayed.
Claim 2
Independent Claim 176 words
A method of processing a video signal in a processing system including a video capture circuit and a video display circuit, the video signal including a sequence of frames each having an even field and an odd field, each of the even field and the odd field including corresponding first and second sets of lines, each set of lines representing a predetermined subset of all lines in a given even or odd field, the method comprising the steps of selecting an odd-numbered decimation factor for use in the video capture circuit to determine the first and second sets of lines from all lines in the even and odd fields; capturing the determined first set of lines in the even field of the video signal during a time period in which the second set of lines in the even field are being displayed; and capturing the determined second set of lines in the odd field of the video signal during a time period in which the first set of lines in the odd field are being displayed.
Claim 3
Independent Claim 206 words
An apparatus for processing a video signal in a processing system, the video signal including a sequence of frames each having an even field and an odd field, each of the even field and the odd field including corresponding first and second sets of lines, each set of lines representing a predetermined subset of all lines in a given even or odd field, the apparatus comprising: a video capture circuit having an input coupled to a video source and receiving the video signal therefrom; and a video display circuit having an input coupled to an output of the video capture circuit; wherein the video capture circuit utilizes an odd-numbered decimation factor to determine the first and second sets of lines from all lines in the even and odd fields, the video capture circuit captures the first set of lines in the even field of the video signal during a time period in which the video display circuit displays the second set of lines in the even field, and the video capture circuit captures the second set of lines in the odd field of the video signal during a time period in which the video display circuit displays the first set of lines in the odd field.
Claim 4
Independent Claim 206 words
An apparatus for processing a video signal in a processing system, the video signal including a sequence of frames each having an even field and an odd field, each of the even field and the odd field including corresponding first and second sets of lines, each set of lines representing a predetermined subset of all lines in a given even or odd field, the apparatus comprising: a video capture circuit having an input coupled to a video source and receiving the video signal therefrom; and a video display circuit having an input coupled to an output of the video capture circuit; wherein the video capture circuit utilizes an odd-numbered decimation factor to determine the first and second sets of lines from all lines in the even and odd fields, the video capture circuit captures the first set of lines in the even field of the video signal during a time period in which the video display circuit displays the second set of lines in the even field, and the video capture circuit captures the second set of lines in the odd field of the video signal during a time period in which the video display circuit displays the first set of lines in the odd field.

References Cited (Backward Citations)

US5504532A Cited
US5510846A Cited
US5469228A Cited
US5539464A Cited
US5684529A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-07-12 2003-01-11 2003-07-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-07-12 2007-01-11 2007-07-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-07-12 2011-01-11 2011-07-13 $7700.00 Window Closed / Lapsed

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