US5930631A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making double-poly MONOS flash EEPROM cell
Assignee: Promos Technologies Inc
•
Filing: 1997-06-12
•
Granted: 1999-07-27
•
Expires: 2017-06-12
Abstract
Abstract The present invention discloses a double poly metal oxide/nitride/oxide semiconductor electrically erasable programmable read only memory (EEPROM) for use in semiconductor memories. The EEPROM structure includes a select gate, an oxide\nitride\oxide layer, and a control gate. The control gate is formed on the oxide\nitride\oxide layer. A lightly doped drain (LDD) structure is formed adjacent to the drain and underneath the control gate.
Inventors
- 👤 Chih-Hsien Wang
- 👤 Min-Liang Chen
- 👤 Thomas Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:26
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/69; H10D30/01; H10D30/021; H10D30/0413; H10D64/00; H10D64/01; H10D64/031; H10D64/037; H10D64/60; H10D64/66; H10D64/68; H10D64/681
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
191 words
A method of fabricating a double-poly MONOS EEPROM on a semiconductor substrate, said method comprising the steps of: forming a first silicon dioxide layer on said semiconductor substrate; forming a first polysilicon layer on said first silicon dioxide layer; patterning a first photoresist on said first polysilicon layer; etching said first polysilicon layer and said first silicon dioxide to form a select gate and a gate oxide; forming a second silicon dioxide layer on said select gate and said substrate; etching said second silicon dioxide layer to form a side wall spacer adjacent to said gate oxide and select gate; forming a lightly doped drain by using ion implantation; removing said side wall spacer; forming a dielectric layer on said select gate and said substrate; forming a second polysilicon layer on said dielectric layer; patterning a second photoresist on said second polysilicon layer; etching said second polysilicon layer and said dielectric layer such that said dielectric layer and said second polysilicon layer extends from said lightly doped drain to a portion of said select gate; and forming a heavily doped source and drain using ion implantation to form said MONOS EEPROM.
Claim 2
Independent Claim
191 words
A method of fabricating a double-poly MONOS EEPROM on a semiconductor substrate, said method comprising the steps of: forming a first silicon dioxide layer on said semiconductor substrate; forming a first polysilicon layer on said first silicon dioxide layer; patterning a first photoresist on said first polysilicon layer; etching said first polysilicon layer and said first silicon dioxide to form a select gate and a gate oxide; forming a second silicon dioxide layer on said select gate and said substrate; etching said second silicon dioxide layer to form a side wall spacer adjacent to said gate oxide and select gate; forming a lightly doped drain by using ion implantation; removing said side wall spacer; forming a dielectric layer on said select gate and said substrate; forming a second polysilicon layer on said dielectric layer; patterning a second photoresist on said second polysilicon layer; etching said second polysilicon layer and said dielectric layer such that said dielectric layer and said second polysilicon layer extends from said lightly doped drain to a portion of said select gate; and forming a heavily doped source and drain using ion implantation to form said MONOS EEPROM.
Claim 3
Dependent Claim
14 words
The method of claim 1, wherein said dielectric layer is composed of oxide\nitride\oxide layer.
Claim 4
Dependent Claim
18 words
The method of claim 2, wherein said oxide\nitride\oxide layer has a thickness of a range of 200-300 angstroms.
Claim 5
Dependent Claim
17 words
The method of claim 2, wherein said second polysilicon layer is used to form a control gate.
References Cited (Backward Citations)
US4098924A
Cited
US4105805A
Cited
US4964080A
Cited
US5326999A
Cited
US5700728A
Cited
US5851881A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-26 | 2003-01-25 | 2003-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-26 | 2007-01-25 | 2007-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-26 | 2011-01-25 | 2011-07-27 | $7700.00 | Window Closed / Lapsed |