US5936880A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bi-layer programmable resistor memory
Assignee: FOOTHILLS IP LLC
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Filing: 1997-11-13
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Granted: 1999-08-10
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Expires: 2017-11-13
Abstract
Abstract A static, in-circuit programmable memory device is provided where the storage element employed is a bi-layer programmable resistor. A specialized programming and readout circuit is provided for each storage element, allowing a known word-line/bit-line memory architecture (commonly used with fuse type memories) to be adapted to a memory element that conducts in both of two different states. The programming and readout circuit may take the form of a merged bipolar/FET device. A bipolar transistor is used for programming and also provides a diode action to prevent sneak path currents from flowing when a storage element is not selected. The bipolar transistor may be a parasitic bipolar transistor. An FET is used for readout. Storage elements are paired, one storage element of each pair functioning as a reference element. The bit lines of the paired storage elements are connected to a current mirror circuit that effects a comparison between current through the reference element and current through its paired storage element. Reliable readout is thereby attained.
Inventors
- 👤 Robert L. Payne
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 10:22
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/16
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
135 words
A memory apparatus comprising: a multiplicity of programmable resistors having at least a low impedance state and a medium impedance state and having first and second terminals, each programmable resistor comprising a layer of doped polysilicon and at least one other layer; a multiplicity of word lines and bit lines coupled to said multiplicity of programmable resistors such that first terminals of a plurality of programmable resistors are coupled to a same word line and second terminals of said plurality of programmable resistors are coupled to respective different bit lines; a multiplicity of access circuits provided in correspondence to said multiplicity of programmable resistors, each of said access circuits comprising a transistor coupled to the second terminal of the corresponding programmable resistor to create a current path to a respective one of said bit lines.
Claim 2
Dependent Claim
135 words
A memory apparatus comprising: a multiplicity of programmable resistors having at least a low impedance state and a medium impedance state and having first and second terminals, each programmable resistor comprising a layer of doped polysilicon and at least one other layer; a multiplicity of word lines and bit lines coupled to said multiplicity of programmable resistors such that first terminals of a plurality of programmable resistors are coupled to a same word line and second terminals of said plurality of programmable resistors are coupled to respective different bit lines; a multiplicity of access circuits provided in correspondence to said multiplicity of programmable resistors, each of said access circuits comprising a transistor coupled to the second terminal of the corresponding programmable resistor to create a current path to a respective one of said bit lines.
Claim 3
Dependent Claim
39 words
The apparatus of claim 1 wherein said transistor is a readout transistor, each of said access circuits further comprising a programming transistor coupled to the second terminal of the corresponding programmable resistor to create a current path to ground.
Claim 4
Dependent Claim
13 words
The apparatus of claim 2 wherein said programming transistor is a bipolar transistor.
Claim 5
Dependent Claim
14 words
The apparatus of claim 3 wherein said readout transistor is a field effect transistor.
Claim 6
Dependent Claim
30 words
The apparatus of claim 4 wherein the programming transistor and the readout transistor are merged in a single device so as to share the same area on an integrated circuit.
Claim 7
Dependent Claim
50 words
The apparatus of claim 5 wherein said single device comprises: a substrate having a first conductivity type; a diffusion well having a second opposite conductivity type; within said diffusion well, first and second diffusion regions of said first conductivity type and a third diffusion region of said second conductivity type.
Claim 8
Dependent Claim
51 words
The apparatus of claim 6, further comprising: emitter and collector electrodes connected to respective ones of said first and second diffusion regions; a base electrode connected to said third diffusion region; and a gate electrode connected in an area between said first and second diffusion regions to define a channel region.
Claim 9
Dependent Claim
73 words
The apparatus of claim 2, wherein said programmable resistors are paired to form a plurality of bit cells, each bit cell comprising: a first programmable resistor in a known impedance state coupled to a first bit line; a second programmable resistor coupled to a second bit line; and means coupled to the first bit line and the second bit line for producing an indication of the impedance state of the second programmable resistor.
Claim 10
Dependent Claim
14 words
The apparatus of claim 8, wherein said means for producing comprises a current mirror.
Claim 11
Dependent Claim
20 words
The apparatus of claim 9, wherein the current mirror has a current gain having a value substantially different than unity.
Claim 12
Independent Claim
95 words
A method of accessing a bit cell of a programmable resistor memory, the bit cell including at least one programmable resistor having first and second terminals and an access circuit including a transistor, the method comprising the steps of: applying a voltage to a first terminal of the programmable resistor; causing the transistor to conduct; and conducting a programming current through the programmable resistor and through the transistor; wherein said access circuit includes both a bipolar transistor and a field effect transistor wherein a preponderance of said programming current is conducted through the bipolar transistor.
Claim 13
Independent Claim
95 words
A method of accessing a bit cell of a programmable resistor memory, the bit cell including at least one programmable resistor having first and second terminals and an access circuit including a transistor, the method comprising the steps of: applying a voltage to a first terminal of the programmable resistor; causing the transistor to conduct; and conducting a programming current through the programmable resistor and through the transistor; wherein said access circuit includes both a bipolar transistor and a field effect transistor wherein a preponderance of said programming current is conducted through the bipolar transistor.
Claim 14
Dependent Claim
48 words
The method of claim 11, comprising the further steps of: applying a voltage to the first terminal of the programmable resistor; applying a voltage to a gate terminal of the field effect transistor; and conducting a readout current through the programmable resistor and through the field effect transistor.
Claim 15
Dependent Claim
72 words
The method of claim 12, wherein said bit cell includes a storage programmable resistor and a reference programmable resistor, and wherein the steps of claim 11 are performed with respect to both the storage programmable resistor and the reference programmable resistor, the method comprising the further step of effecting a relative comparison of a readout current obtained through the storage programmable resistor and a readout current obtained through the reference programmable resistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-09 | 2003-02-08 | 2003-08-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-09 | 2007-02-08 | 2007-08-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-09 | 2011-02-08 | 2011-08-10 | $7700.00 | Window Closed / Lapsed |