US5937190A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Architecture and methods for a hardware description language source level analysis and debugging system
Assignee: Synopsys Inc
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Filing: 1995-04-03
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Granted: 1999-08-10
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Expires: 2015-04-03
Abstract
Abstract A digital circuit is synthesized from a text description of a digital system. During synthesis, a parse tree with parse nodes is constructed and retained. The relationship between the parse nodes and the circuit elements synthesized from those parse nodes is retained. Using that relationship, analysis results associated with circuit elements can be related to the text that generated those circuit elements. In particular, the analysis results can be used to set the display characteristics, such as font or size, of the text associated with those results.
Inventors
- 👤 Brent Gregory
- 👤 Trinanjan Chatterjee
- 👤 Jing C. Lin
- 👤 Srinivas Raghvendra
- 👤 Emil Girczyc
- 👤 Paul Estrada
- 👤 Andrew Seawright
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:06
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/323; G06F2119/00; G06F2119/06
Claims Analysis
Total Claims: 76
Claim 1
Independent Claim
171 words
A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising: a parse generator generating a parse data structure stored in a memory of the system, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description; a digital Gtech circuit representation generator generating a digital Gtech circuit representation stored in the memory, the digital Gtech circuit representation synthesized from the parse data structure and including a Gtech circuit element, the Gtech circuit element referring to the parse node, wherein the parse node also refers to the Gtech circuit element; and wherein the portion of the text description, related to the Gtech circuit element, can be determined by following the reference from the Gtech circuit element to the parse node and the reference from the parse node to the portion of the text description.
Claim 2
Dependent Claim
171 words
A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising: a parse generator generating a parse data structure stored in a memory of the system, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description; a digital Gtech circuit representation generator generating a digital Gtech circuit representation stored in the memory, the digital Gtech circuit representation synthesized from the parse data structure and including a Gtech circuit element, the Gtech circuit element referring to the parse node, wherein the parse node also refers to the Gtech circuit element; and wherein the portion of the text description, related to the Gtech circuit element, can be determined by following the reference from the Gtech circuit element to the parse node and the reference from the parse node to the portion of the text description.
Claim 3
Dependent Claim
164 words
A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising: a parse generator generating a parse data structure stored in a memory, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description; a digital circuit representation generator generating a digital circuit representation stored in the memory, the digital circuit representation synthesized from the parse data structure and including a first circuit element, the first circuit element referring to the parse node, wherein the parse node also refers to the first circuit element; and wherein the portion of the text description, related to first circuit element, can be determined by following the reference from the first circuit element to the parse node and the reference from the parse node to the portion of the text description.
Claim 4
Dependent Claim
164 words
A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising: a parse generator generating a parse data structure stored in a memory, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description; a digital circuit representation generator generating a digital circuit representation stored in the memory, the digital circuit representation synthesized from the parse data structure and including a first circuit element, the first circuit element referring to the parse node, wherein the parse node also refers to the first circuit element; and wherein the portion of the text description, related to first circuit element, can be determined by following the reference from the first circuit element to the parse node and the reference from the parse node to the portion of the text description.
Claim 5
Dependent Claim
15 words
The computer-aided circuit analysis tool of claim 2, wherein said circuit design language is Verilog.
Claim 6
Dependent Claim
15 words
The computer-aided circuit analysis tool of claim 2, wherein said circuit design language is VHDL.
Claim 7
Dependent Claim
163 words
A computer-aided circuit analysis, tool for analyzing a text description of a digital system written in a circuit design language, comprising: a parse generator generating a parse data structure stored in a memory in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description; a digital circuit representation generator generating a digital circuit representation stored in the memory, the digital circuit representation synthesized from the parse data structure and including a first circuit element, the first circuit element referring to the parse node, wherein the parse node also refers to the first circuit element; a numerical physical characteristic of said first circuit element, stored in the memory; and a computer window generator causing to be displayed a visual object linked to said parse node and having a visual display characteristic determined by said numerical physical characteristic.
Claim 8
Dependent Claim
163 words
A computer-aided circuit analysis, tool for analyzing a text description of a digital system written in a circuit design language, comprising: a parse generator generating a parse data structure stored in a memory in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description; a digital circuit representation generator generating a digital circuit representation stored in the memory, the digital circuit representation synthesized from the parse data structure and including a first circuit element, the first circuit element referring to the parse node, wherein the parse node also refers to the first circuit element; a numerical physical characteristic of said first circuit element, stored in the memory; and a computer window generator causing to be displayed a visual object linked to said parse node and having a visual display characteristic determined by said numerical physical characteristic.
Claim 9
Dependent Claim
41 words
The computer-aided circuit analysis tool of claim 5, wherein said first circuit element includes one or more circuit parts, with each circuit part possessing an area, and said numerical physical characteristic is the sum of the areas of said circuit parts.
Claim 10
Dependent Claim
41 words
The computer-aided circuit analysis tool of claim 5, wherein said first circuit element includes a circuit part input pin and a primary input, and said numerical physical characteristic is a time delay from said primary input to said circuit part pin.
Claim 11
Dependent Claim
25 words
The computer-aided circuit analysis tool of claim 5, wherein said visual object is a rectangle having a height, said visual display characteristic being said height.
Claim 12
Dependent Claim
28 words
The computer-aided circuit analysis tool of claim 5, wherein said visual object is a text character said visual display characteristic is a displayed font of said text character.
Claim 13
Dependent Claim
29 words
The computer-aided circuit analysis tool of claim 5, wherein said visual object is a text character and said visual display characteristic is a displayed color of said text character.
Claim 14
Dependent Claim
15 words
The computer-aided circuit analysis tool of claim 5, wherein said circuit design language is Verilog.
Claim 15
Dependent Claim
15 words
The computer-aided circuit analysis tool of claim 5, wherein said circuit design language is VHDL.
Claim 16
Dependent Claim
169 words
A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising: a parse generator generating a parse data structure stored in a memory, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description; a digital circuit representation generator generating a digital circuit representation stored in the memory, the digital circuit representation synthesized from the parse data structure and including a first circuit element, the first circuit element referring to the parse node, wherein the parse node also refers to the first circuit element; a first display window generator causing to be displayed in a first display window, a first display object linked to said parse node; and a second display window generator, causing to be displayed in a second display window, a second display object linked to said first circuit element.
Claim 17
Dependent Claim
169 words
A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising: a parse generator generating a parse data structure stored in a memory, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description; a digital circuit representation generator generating a digital circuit representation stored in the memory, the digital circuit representation synthesized from the parse data structure and including a first circuit element, the first circuit element referring to the parse node, wherein the parse node also refers to the first circuit element; a first display window generator causing to be displayed in a first display window, a first display object linked to said parse node; and a second display window generator, causing to be displayed in a second display window, a second display object linked to said first circuit element.
Claim 18
Dependent Claim
48 words
The computer-aided circuit analysis tool of claim 13, wherein said first display object includes a sequence of one or more characters from said text description, and wherein said sequence of characters includes a subsequence of characters related to said parse node in accordance with said circuit description language.
Claim 19
Dependent Claim
34 words
The computer-aided circuit analysis tool of claim 14, wherein said subsequence of characters is displayed with a visual characteristic distinct from the visual characteristic of said sequence of characters not included in said subsequence.
Claim 20
Dependent Claim
37 words
The computer-aided circuit analysis tool of claim 13, wherein said first display object includes a sequence of one or more characters from said text description related to said parse node in accordance with said circuit description language.
Claim 21
Dependent Claim
15 words
The computer-aided circuit analysis tool of claim 13, wherein said circuit design language is Verilog.
Claim 22
Dependent Claim
15 words
The computer-aided circuit analysis tool of claim 13, wherein said circuit design language is VHDL.
Claim 23
Dependent Claim
181 words
A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising: a parse generator generating a parse data structure stored in a memory, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description; a digital circuit representation generator generating a digital circuit representation stored in the memory, the digital circuit representation synthesized from the parse data structure and including a first circuit element, the first circuit element referring to the parse node, wherein the parse node also refers to the first circuit element; and an optimizer that optimizes the digital circuit representation, yielding a mapped circuit representation stored in the memory, the mapped digital circuit representation including a second circuit element, the second circuit element referring to one of said parse node or said first circuit element, so that there is a traceable path between the second circuit element and the parse node.
Claim 24
Dependent Claim
181 words
A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising: a parse generator generating a parse data structure stored in a memory, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description; a digital circuit representation generator generating a digital circuit representation stored in the memory, the digital circuit representation synthesized from the parse data structure and including a first circuit element, the first circuit element referring to the parse node, wherein the parse node also refers to the first circuit element; and an optimizer that optimizes the digital circuit representation, yielding a mapped circuit representation stored in the memory, the mapped digital circuit representation including a second circuit element, the second circuit element referring to one of said parse node or said first circuit element, so that there is a traceable path between the second circuit element and the parse node.
Claim 25
Dependent Claim
24 words
The computer-aided circuit analysis tool of claim 19, wherein there is a traceable path between the second circuit element and the first circuit element.
Claim 26
Dependent Claim
155 words
A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising: a parse generator generating a parse data structure stored in a memory, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description; a digital circuit representation generator generating a digital circuit representation stored in the memory, the digital circuit representation synthesized from the parse data structure and including a circuit element, the circuit element referring to the parse node, wherein the parse node also refers to the circuit element; and a stacked bar graph window display generator causing a stacked bar graph to be displayed on a display screen, the stacked bar graph representing a numerical physical characteristic of the circuit element, stored in the memory.
Claim 27
Dependent Claim
155 words
A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising: a parse generator generating a parse data structure stored in a memory, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description; a digital circuit representation generator generating a digital circuit representation stored in the memory, the digital circuit representation synthesized from the parse data structure and including a circuit element, the circuit element referring to the parse node, wherein the parse node also refers to the circuit element; and a stacked bar graph window display generator causing a stacked bar graph to be displayed on a display screen, the stacked bar graph representing a numerical physical characteristic of the circuit element, stored in the memory.
Claim 28
Dependent Claim
21 words
The computer-aided circuit analysis tool of claim 21, wherein the numerical physical characteristic represented by the stacked bar graph is power.
Claim 29
Dependent Claim
21 words
The computer-aided circuit analysis tool of claim 21, wherein the numerical physical characteristic represented by the stacked bar graph is area.
Claim 30
Dependent Claim
22 words
The computer-aided circuit analysis tool of claim 21, wherein the numerical physical characteristic represented by the stacked bar graph is logic levels.
Claim 31
Dependent Claim
38 words
The computer-aided circuit analysis tool of claim 21, further comprising: a text window display generator causing a portion of the text description that is traceable to the stacked bar graph to be displayed with a different physical property.
Claim 32
Dependent Claim
31 words
The computer-aided circuit analysis tool of claim 25, wherein the entire portion of the text description that is traceable to the stacked bar graph is displayed with a predetermined physical property.
Claim 33
Dependent Claim
69 words
The computer-aided circuit analysis tool of claim 25, further comprising: a user input receiver that receives an indication that a user has selected a portion of the stacked bar graph; wherein the text window display generator causes a portion of the text description that is traceable to the selected portion of the stacked bar graph to be displayed with the predetermined physical property in accordance with the user selection.
Claim 34
Dependent Claim
75 words
The computer-aided circuit analysis tool of claim 25, further comprising a user input receiver that receives an indication that a user has selected a portion of the stacked bar graph; wherein the stacked bar graph window display generator causes a second stacked bar graph to be displayed on a display screen in accordance with the user selection, the second stacked bar graph representing the numerical physical characteristic of a lower hierarchy of said circuit element.
Claim 35
Dependent Claim
62 words
The computer-aided circuit analysis tool of claim 21, a user input receiver that receives an indication that a user has selected a portion of the displayed text description; wherein the stacked bar graph window generator causes to be displayed a stacked bar graph that is traceable to the selected portion of the text description in accordance with the selection of the user.
Claim 36
Dependent Claim
174 words
A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising: a parse generator generating a parse data structure stored in a memory, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description; a digital circuit representation generator generating a digital circuit representation, stored in the memory, the digital circuit representation synthesized from the parse data structure and including a plurality of circuit elements, at least one of the plurality of circuit elements referring to the parse node, wherein the parse node also refers to the at least one circuit element; and a path browser window display generator, causing at least one circuit element, along a first path through a digital circuit representation of the digital system, to be summarized such that only its input and output which are part of the first path are displayed.
Claim 37
Dependent Claim
174 words
A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising: a parse generator generating a parse data structure stored in a memory, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description; a digital circuit representation generator generating a digital circuit representation, stored in the memory, the digital circuit representation synthesized from the parse data structure and including a plurality of circuit elements, at least one of the plurality of circuit elements referring to the parse node, wherein the parse node also refers to the at least one circuit element; and a path browser window display generator, causing at least one circuit element, along a first path through a digital circuit representation of the digital system, to be summarized such that only its input and output which are part of the first path are displayed.
Claim 38
Dependent Claim
18 words
The computer-aided circuit analysis tool of claim 30, wherein the digital circuit representation is a Gtech circuit representation.
Claim 39
Dependent Claim
19 words
The computer-aided circuit analysis tool of claim 30, wherein the digital circuit representation is a gate level circuit representation.
Claim 40
Dependent Claim
38 words
The computer-aided circuit analysis tool of claim 30, further comprising: a text window display generator, causing a portion of the text description that is traceable to the digital circuit representation to be displayed with a predetermined physical property.
Claim 41
Dependent Claim
31 words
The computer-aided circuit analysis tool of claim 33, wherein the entire portion of the text description that is traceable to the digital circuit representation is displayed with the predetermined physical property.
Claim 42
Dependent Claim
69 words
The computer-aided circuit analysis tool of claim 33, further comprising: a user input receiver that receives an indication that a user has selected a portion of the path browser summary; wherein the text window display generator causes a portion of the text description that is traceable to the selected portion of the path browser summary to be displayed with a predetermined physical property in accordance with the user selection.
Claim 43
Dependent Claim
61 words
The computer-aided circuit analysis tool of claim 35, a user input receiver that receives an indication that a user has selected a portion of the displayed text description; wherein the path browser window generator causes to be displayed a path browser summary that is traceable to the selected portion of the text description in accordance with the selection of the user.
Claim 44
Dependent Claim
60 words
The computer-aided circuit analysis tool of claim 30, a user input receiver that receives an indication that a user has selected a portion of the path browser summary; wherein the text window generator causes to be displayed a text summary that is traceable to the selected portion of the path browser summary in accordance with the selection of the user.
Claim 45
Dependent Claim
58 words
The computer-aided circuit analysis tool of claim 30, further comprising: a user input receiver that receives an indication that a user has indicated a "start/end" path in the circuit representation; and a text window display generator, causing a portion of the text description that is traceable to the start/end path to be displayed with a predetermined physical property.
Claim 46
Dependent Claim
159 words
A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising: a parse generator generating a parse data structure stored in a memory system, in accordance with the text description the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description; a digital circuit representation generator generating a digital circuit representation, stored in the memory, the digital circuit representation synthesized from the parse data structure and including a circuit element, the circuit element referring to the parse node, wherein the parse node also refers to the circuit element; and a virtual schematic window generator, causing a virtual schematic to be displayed on a display screen, the virtual schematic displaying the text of at least one of a fanin or fanout of a user-selected portion of the text description.
Claim 47
Dependent Claim
159 words
A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising: a parse generator generating a parse data structure stored in a memory system, in accordance with the text description the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description; a digital circuit representation generator generating a digital circuit representation, stored in the memory, the digital circuit representation synthesized from the parse data structure and including a circuit element, the circuit element referring to the parse node, wherein the parse node also refers to the circuit element; and a virtual schematic window generator, causing a virtual schematic to be displayed on a display screen, the virtual schematic displaying the text of at least one of a fanin or fanout of a user-selected portion of the text description.
Claim 48
Dependent Claim
49 words
The computer-aided circuit analysis tool of claim 39, further comprising: a text window display generator, causing a portion of the text description that is traceable to one of the fan ins and fanouts of the selection portion of the circuit representation to be displayed with a predetermined physical property.
Claim 49
Dependent Claim
30 words
The computer-aided circuit analysis tool of claim 40, wherein the entire portion of the text description that is traceable to the circuit representation is displayed with the predetermined physical property.
Claim 50
Dependent Claim
67 words
The computer-aided circuit analysis tool of claim 40, further comprising: a user input receiver that receives an indication that a user has selected a displayed fanin or fanout; wherein the text window display generator causes a portion of the text description that is traceable to the selected portion of the fanin or fanout to be displayed with a predetermined physical property in accordance with the user selection.
Claim 51
Dependent Claim
69 words
The computer-aided circuit analysis tool of claim 40, a user input receiver that receives an indication that a user has selected a portion of the displayed text description; wherein the virtual schematic window generator causes to be displayed a portion of the circuit representation, along with its fanins and fanouts that is traceable to the selected portion of the text description in accordance with the selection of the user.
Claim 52
Dependent Claim
215 words
A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising: a memory storing; a parse tree stored in a memory of the system, in accordance with the text description, the parse tree including a parse tree node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description; at least one digital circuit representation stored in the memory, the at least one digital circuit representation synthesized from the parse tree and including a circuit element the circuit element referring to the parse tree node, wherein the parse node also refers to the circuit element, the at least one circuit representation being stored in one or more different circuit domains; a plurality of analysis tools each analysis tool capable of performing analysis on one or more of the circuit domains; a plurality of display tools, each display tool capable of displaying data from one or more circuit domains; a domain mapper, capable of mapping between ones of the plurality of circuit domains; and a selection manager that informs the plurality of display tools when a user has selected a displayed element of the circuit representation within a one of the display tools.
Claim 53
Dependent Claim
215 words
A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising: a memory storing; a parse tree stored in a memory of the system, in accordance with the text description, the parse tree including a parse tree node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description; at least one digital circuit representation stored in the memory, the at least one digital circuit representation synthesized from the parse tree and including a circuit element the circuit element referring to the parse tree node, wherein the parse node also refers to the circuit element, the at least one circuit representation being stored in one or more different circuit domains; a plurality of analysis tools each analysis tool capable of performing analysis on one or more of the circuit domains; a plurality of display tools, each display tool capable of displaying data from one or more circuit domains; a domain mapper, capable of mapping between ones of the plurality of circuit domains; and a selection manager that informs the plurality of display tools when a user has selected a displayed element of the circuit representation within a one of the display tools.
Claim 54
Dependent Claim
37 words
The circuit analysis tool of claim 44, wherein one of the plurality of display tools is a display tool capable of displaying data from the at least one of the source domain and the circuit representation domain.
Claim 55
Dependent Claim
171 words
A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising: a parse generator generating a parse data structure stored in a memory of the system, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description; a digital Gtech circuit representation generator generating a digital Gtech circuit representation stored in the memory, the digital Gtech circuit representation synthesized from the parse data structure and including a Gtech circuit element, the Gtech circuit element referring to the parse node, wherein the parse node also refers to the Gtech circuit element; and wherein the Gtech circuit element, related to the portion of the text description, can be determined by following the reference from the portion of the text description to the parse node and the reference from the parse node to the Gtech circuit element.
Claim 56
Dependent Claim
171 words
A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising: a parse generator generating a parse data structure stored in a memory of the system, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description; a digital Gtech circuit representation generator generating a digital Gtech circuit representation stored in the memory, the digital Gtech circuit representation synthesized from the parse data structure and including a Gtech circuit element, the Gtech circuit element referring to the parse node, wherein the parse node also refers to the Gtech circuit element; and wherein the Gtech circuit element, related to the portion of the text description, can be determined by following the reference from the portion of the text description to the parse node and the reference from the parse node to the Gtech circuit element.
Claim 57
Dependent Claim
165 words
A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising: a parse generator generating a parse data structure stored in a memory, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description; a digital circuit representation generator generating a digital circuit representation stored in the memory, the digital circuit representation synthesized from the parse data structure and including a first circuit element, the first circuit element referring to the parse node, wherein the parse node also refers to the first circuit element; and wherein the first circuit element, related to the portion of the text description, can be determined by following the reference from the portion of the text description to the parse node and the reference from the parse node to the first circuit element.
Claim 58
Dependent Claim
165 words
A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising: a parse generator generating a parse data structure stored in a memory, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description; a digital circuit representation generator generating a digital circuit representation stored in the memory, the digital circuit representation synthesized from the parse data structure and including a first circuit element, the first circuit element referring to the parse node, wherein the parse node also refers to the first circuit element; and wherein the first circuit element, related to the portion of the text description, can be determined by following the reference from the portion of the text description to the parse node and the reference from the parse node to the first circuit element.
Claim 59
Dependent Claim
15 words
The computer-aided circuit analysis tool of claim 47, wherein said circuit design language is Verilog.
Claim 60
Dependent Claim
15 words
The computer-aided circuit analysis tool of claim 47, wherein said circuit design language is VHDL.
Claim 61
Dependent Claim
52 words
The computer-aided circuit analysis tool of claim 47, further comprising: a numerical physical characteristic of said first circuit element, stored in the memory; and a computer window generator causing to be displayed a visual object linked to said parse node and having a visual display characteristic determined by said numerical physical characteristic.
Claim 62
Dependent Claim
41 words
The computer-aided circuit analysis tool of claim 50, wherein said first circuit element includes one or more circuit parts, with each circuit part possessing an area, and said numerical physical characteristic is the sum of the areas of said circuit parts.
Claim 63
Dependent Claim
41 words
The computer-aided circuit analysis tool of claim 50, wherein said first circuit element includes a circuit part input pin and a primary input, and said numerical physical characteristic is a time delay from said primary input to said circuit part pin.
Claim 64
Dependent Claim
25 words
The computer-aided circuit analysis tool of claim 50, wherein said visual object is a rectangle having a height, said visual display characteristic being said height.
Claim 65
Dependent Claim
28 words
The computer-aided circuit analysis tool of claim 50, wherein said visual object is a text character said visual display characteristic is a displayed font of said text character.
Claim 66
Dependent Claim
29 words
The computer-aided circuit analysis tool of claim 50, wherein said visual object is a text character and said visual display characteristic is a displayed color of said text character.
Claim 67
Dependent Claim
15 words
The computer-aided circuit analysis tool of claim 50, wherein said circuit design language is Verilog.
Claim 68
Dependent Claim
15 words
The computer-aided circuit analysis tool of claim 50, wherein said circuit design language is VHDL.
Claim 69
Dependent Claim
58 words
The computer-aided circuit analysis tool of claim 47, further comprising: a first display window generator causing to be displayed in a first display window, a first display object linked to said parse node; and a second display window generator, causing to be displayed in a second display window, a second display object linked to said first circuit element.
Claim 70
Dependent Claim
48 words
The computer-aided circuit analysis tool of claim 58, wherein said first display object includes a sequence of one or more characters from said text description; and wherein said sequence of characters includes a subsequence of characters related to said parse node in accordance with said circuit description language.
Claim 71
Dependent Claim
34 words
The computer-aided circuit analysis tool of claim 57, wherein said subsequence of characters is displayed with a visual characteristic distinct from the visual characteristic of said sequence of characters not included in said subsequence.
Claim 72
Dependent Claim
37 words
The computer-aided circuit analysis tool of claim 58, wherein said first display object includes a sequence of one or more characters from said text description related to said parse node in accordance with said circuit description language.
Claim 73
Dependent Claim
15 words
The computer-aided circuit analysis tool of claim 58, wherein said circuit design language is Verilog.
Claim 74
Dependent Claim
15 words
The computer-aided circuit analysis tool of claim 58, wherein said circuit design language is VHDL.
Claim 75
Dependent Claim
66 words
The tool of claim 47, further comprising: an optimizer that optimizes the digital circuit representation, yielding a mapped circuit representation stored in the memory, the mapped digital circuit representation including a second circuit element, the second circuit element referring to one of said parse node or said first circuit element, so that there is a traceable path between the second circuit element and the parse node.
Claim 76
Dependent Claim
24 words
The computer-aided circuit analysis tool of claim 64, wherein there is a traceable path between the second circuit element and the first circuit element.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-09 | 2003-02-08 | 2003-08-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-09 | 2007-02-08 | 2007-08-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-09 | 2011-02-08 | 2011-08-10 | $7700.00 | Window Closed / Lapsed |