Process induced charging damage control device

Claim 2

A plasma charging damage protection structure, comprising: a first conduction path for conducting positive plasma charging away from a device needing protection; a second conduction path for conducting negative plasma charging away from the device needing protection; and a plasma charging enhancement structure coupled to the protection structure, wherein the enhancement structure increases the sensitivity of the protection structure and aids in conducting the plasma charging away from the device needing protection before the plasma charging causes plasma charging damage, wherein the plasma charging enhancement structure comprises an antenna.

Claim 3

The plasma charging damage protection structure of claim 1, wherein the antenna comprises a comb-like antenna having a plurality of fingers.

Claim 4

A plasma charging damage protection circuit, comprising: a transistor needing protection having a gate terminal that is susceptible to plasma charging damage during processing; a protection structure coupled to the gate terminal of the transistor, wherein the protection structure senses plasma charging and conducts positive plasma charging away from the gate terminal through a first conduction path and conducts negative plasma charging away from the terminal through a second conduction path, wherein the transistor needing protection comprises an NMOS transistor and the protection structure comprises an NMOS transistor protection structure having a source terminal coupled to the gate terminal of the transistor needing protection, a drain terminal coupled to a substantially fixed voltage potential, and a gate terminal that is exposed to a plasma during processing, thereby making the gate terminal plasma gated; and a plasma charging enhancement structure coupled to the gate terminal of the NMOS transistor protection structure, thereby increasing a sensitivity of the NMOS transistor protection structure to the plasma charging.

Claim 5

A plasma charging damage protection circuit, comprising: a transistor needing protection having a gate terminal that is susceptible to plasma charging damage during processing; a protection structure coupled to the gate terminal of the transistor, wherein the protection structure senses plasma charging and conducts positive plasma charging away from the gate terminal through a first conduction path and conducts negative plasma charging away from the terminal through a second conduction path, wherein the transistor needing protection comprises an NMOS transistor and the protection structure comprises an NMOS transistor protection structure having a source terminal coupled to the gate terminal of the transistor needing protection, a drain terminal coupled to a substantially fixed voltage potential, and a gate terminal that is exposed to a plasma during processing, thereby making the gate terminal plasma gated; and a plasma charging enhancement structure coupled to the gate terminal of the NMOS transistor protection structure, thereby increasing a sensitivity of the NMOS transistor protection structure to the plasma charging.

Claim 6

The plasma charging damage protection circuit of claim 3, wherein the plasma charging enhancement structure comprises an antenna.

Claim 7

The plasma charging damage protection circuit of claim 4, wherein the antenna comprises a comb-like antenna having a plurality of fingers.

Claim 8

A plasma charging damage protection circuit, comprising: a transistor needing protection having a gate terminal that is susceptible to plasma charging damage during processing; a protection structure coupled to the gate terminal of the transistor, wherein the protection structure senses plasma charging and conducts positive plasma charging away from the gate terminal through a first conduction path and conducts negative plasma charging away from the terminal through a second conduction path. wherein the transistor needing protection comprises a PMOS transistor and the protection structure comprises a PMOS transistor protection structure having a source terminal coupled to the gate terminal of the transistor needing protection, a drain terminal coupled to a substantially fixed voltage potential, and a gate terminal that is exposed to a plasma during processing, thereby making the gate terminal plasma gated, and a plasma charging enhancement structure coupled to the gate terminal of the PMOS transistor protection structure, thereby increasing a sensitivity of the PMOS transistor protection structure to the plasma charging.

Claim 9

A plasma charging damage protection circuit, comprising: a transistor needing protection having a gate terminal that is susceptible to plasma charging damage during processing; a protection structure coupled to the gate terminal of the transistor, wherein the protection structure senses plasma charging and conducts positive plasma charging away from the gate terminal through a first conduction path and conducts negative plasma charging away from the terminal through a second conduction path. wherein the transistor needing protection comprises a PMOS transistor and the protection structure comprises a PMOS transistor protection structure having a source terminal coupled to the gate terminal of the transistor needing protection, a drain terminal coupled to a substantially fixed voltage potential, and a gate terminal that is exposed to a plasma during processing, thereby making the gate terminal plasma gated, and a plasma charging enhancement structure coupled to the gate terminal of the PMOS transistor protection structure, thereby increasing a sensitivity of the PMOS transistor protection structure to the plasma charging.

Claim 10

The plasma charging damage protection circuit of claim 6, wherein the plasma charging enhancement structure comprises an antenna.

Claim 11

The plasma charging damage protection circuit of claim 7, wherein the antenna comprises a comb-like antenna having a plurality of fingers.