US5969990A
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US
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Nonvolatile memory array with NAND string memory cell groups selectively connected to sub bit lines
Assignee: Sony Corp
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Filing: 1998-01-29
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Granted: 1999-10-19
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Expires: 2018-01-29
Abstract
Abstract A semiconductor nonvolatile memory device where a main bit line is divided into a plurality of sub bit lines via operational connecting means, memory transistors connected to the sub bit lines are arranged in the form of a matrix, and control gate electrodes of these memory transistors are connected to word lines, provided with a means for setting sub bit lines at a programming prohibit potential at the time of a data programming operation; a means for causing a discharge in a selected sub bit line among the sub bit lines set to the programming prohibit potential and placing the non-selected sub bit lines among the sub bit lines in a floating state; and a means for supplying a program voltage to the selected word line.
Inventors
- 👤 Kenshiro Arase
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 07:06
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12; G11C16/04; G11C16/0483; G11C16/24; G11C7/00; G11C7/18; H; H10; H10B; H10B69/00
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
130 words
A semiconductor nonvolatile memory device, comprising: a plurality of main bit lines each divided into a plurality of sub bit lines via selective connecting means, a plurality of word lines, a plurality of memory transistors connected to the sub bit lines and arranged in a matrix, wherein control gate electrodes of these memory transistors are each connected to one of said word lines; a booster circuit for selectively setting said sub bit lines at a programming prohibit potential during a data programming operation; and a memory control circuit for causing a discharge in a selected sub bit line and placing all other non-selected sub bit lines in a floating state, during said data programming operation; wherein said memory control circuit then supplies a program voltage to a selected word line.
Claim 2
Dependent Claim
130 words
A semiconductor nonvolatile memory device, comprising: a plurality of main bit lines each divided into a plurality of sub bit lines via selective connecting means, a plurality of word lines, a plurality of memory transistors connected to the sub bit lines and arranged in a matrix, wherein control gate electrodes of these memory transistors are each connected to one of said word lines; a booster circuit for selectively setting said sub bit lines at a programming prohibit potential during a data programming operation; and a memory control circuit for causing a discharge in a selected sub bit line and placing all other non-selected sub bit lines in a floating state, during said data programming operation; wherein said memory control circuit then supplies a program voltage to a selected word line.
Claim 3
Dependent Claim
74 words
The semiconductor nonvolatile memory device according to claim 1, having a NAND string configuration in which a plurality of said memory transistors are connected in series along each of said sub bit lines, wherein a first selection transistor is connected in series between one of said sub bit lines and said series of memory transistors, and a second selection transistor is connected in series between said series of memory transistors and a precharging line.
Claim 4
Dependent Claim
62 words
The semiconductor nonvolatile memory device according to claim 1, wherein said memory transistors are grouped into NAND strings in each of which a plurality of said memory transistors are connected in series; and wherein said booster circuit only sets said selected sub bit line to said programming prohibit potential during a data programming operation, all other, nonselected sub bit lines are unaffected.
Claim 5
Dependent Claim
93 words
The semiconductor nonvolatile memory device according to claim 3, wherein: said main bit lines are individually connected to separate data latch circuits; and at the time of said data programming operation, page program data is transferred to said data latch circuits, and a potential of a NAND string channel portion in which a selected memory transistor exists and the programming prohibit potential charged in the sub bit line to which the NAND string containing the selected memory transistor is connected are discharged to a corresponding main bit line according to the latched data.
Claim 6
Dependent Claim
51 words
The semiconductor nonvolatile memory device according to claim 3, wherein: said sub bit lines are each connected to one of said main bit lines via a first connection transistor and connected to a precharging line, for charging the sub bit line to the programming prohibit potential, via a second connection transistor.
Claim 7
Dependent Claim
38 words
The semiconductor nonvolatile memory device according to claim 5 wherein: said first connection transistor and second connection transistor are connected at their respective gate electrodes to a first connection control line and a second connection control line, respectively.
Claim 8
Dependent Claim
87 words
The semiconductor nonvolatile memory device according to claim 6, wherein: floating gate electrodes of said memory transistors are formed by a first conductive layer film; said word lines to which the control gate electrodes of said memory transistors are connected, and said first connection control line and second connection control line are formed by a second conductive layer film; said sub bit lines and precharging line are formed by a third conductive layer film; and said main bit lines are formed by a fourth conductive layer film.
Claim 9
Dependent Claim
62 words
The semiconductor nonvolatile memory device according to claim 7, wherein: said first conductive layer film is a first polycrystalline silicon layer; said second conductive layer film is a second polycrystalline silicon layer or polycrystalline silicide layer; said third conductive layer film is a third polycrystalline silicon layer or a polycrystalline silicide layer; and said fourth conductive layer film is an aluminum layer.
Claim 10
Independent Claim
150 words
A method of data programming of a NAND type semiconductor nonvolatile memory device wherein a plurality of main bit lines are each divided into a plurality of sub bit lines via operational connecting means, serial strings of memory transistors which are electrically programmed are connected in series between one of said sub bit lines and a ground line via selection transistors to constitute NAND strings, and the NAND strings are arranged in a matrix, the method comprising: selecting a sub bit line connected to a selected NAND string and boosting a potential of a channel portion of said selected NAND string to a programming prohibit potential using said selected sub bit line; discharging said selected sub bit line to the main bit line according to data to be programmed, while placing all non-selected sub bit lines in a floating state; and supplying a program voltage to said selected word line.
Claim 11
Independent Claim
150 words
A method of data programming of a NAND type semiconductor nonvolatile memory device wherein a plurality of main bit lines are each divided into a plurality of sub bit lines via operational connecting means, serial strings of memory transistors which are electrically programmed are connected in series between one of said sub bit lines and a ground line via selection transistors to constitute NAND strings, and the NAND strings are arranged in a matrix, the method comprising: selecting a sub bit line connected to a selected NAND string and boosting a potential of a channel portion of said selected NAND string to a programming prohibit potential using said selected sub bit line; discharging said selected sub bit line to the main bit line according to data to be programmed, while placing all non-selected sub bit lines in a floating state; and supplying a program voltage to said selected word line.
Claim 12
Dependent Claim
130 words
A nonvolatile memory device comprising: a plurality of main bit lines, wherein each main bit line is connected to a plurality of sub bit lines; a control connection transistor connected between each said sub bit line and a respective main bit line; a plurality of memory transistors arranged in groups, each such group of memory transistors comprising a plurality of memory transistors connected in series, and each such series of memory transistors beginning and ending with a selection transistor connected in series with said series of memory transistors, wherein each said sub bit line comprises a plurality of said groups of memory transistors; a plurality of word lines connected to gate electrodes of said memory transistors; and a plurality of selection lines connected to gate electrodes of said selection transistors.
Claim 13
Dependent Claim
130 words
A nonvolatile memory device comprising: a plurality of main bit lines, wherein each main bit line is connected to a plurality of sub bit lines; a control connection transistor connected between each said sub bit line and a respective main bit line; a plurality of memory transistors arranged in groups, each such group of memory transistors comprising a plurality of memory transistors connected in series, and each such series of memory transistors beginning and ending with a selection transistor connected in series with said series of memory transistors, wherein each said sub bit line comprises a plurality of said groups of memory transistors; a plurality of word lines connected to gate electrodes of said memory transistors; and a plurality of selection lines connected to gate electrodes of said selection transistors.
Claim 14
Dependent Claim
24 words
The nonvolatile memory device of claim 10, further comprising a row decoder controlling said control connection transistors, said word lines and said selection lines.
Claim 15
Dependent Claim
25 words
The nonvolatile memory device of claim 11, further comprising a booster circuit providing a programming voltage and a programming prohibit voltage to said row decoder.
Claim 16
Dependent Claim
22 words
The nonvolatile memory device of claim 10, wherein each of said main bit lines is connected to a separate data latch circuit.
Claim 17
Dependent Claim
28 words
The nonvolatile memory device of claim 10, further comprising a precharging line, wherein each sub bit line is connected to said precharging line through a connection control transistor.
Claim 18
Dependent Claim
50 words
The nonvolatile memory device of claim 14, further comprising a booster circuit and a row decoder, wherein said booster circuit provides a programming voltage and a programming prohibit voltage to said row decoder and a precharging voltage to said precharging line, said row decoder controlling said word and selection lines.
Claim 19
Dependent Claim
47 words
The nonvolatile memory device of claim 10, wherein a group of memory and selection transistors on a first sub bit line and a group of memory and selection transistors on a second sub bit line are both connected to a single set of word and selection lines.
Claim 20
Dependent Claim
23 words
The nonvolatile memory device of claim 16, wherein said first and second sub bit lines are connected to a single main bit line.
Claim 21
Dependent Claim
22 words
The nonvolatile memory device of claim 16, wherein said first and second sub bit lines are connected to different main bit lines.
Claim 22
Independent Claim
166 words
A method of programming a nonvolatile memory device comprising: controlling connections between a main bit line and a plurality of sub bit lines with connection control transistors; controlling connections between a plurality of groups of memory transistors and each of sad sub bit lines with a selection transistor, wherein each said group of memory transistors comprises a plurality of memory transistors connected in series, said series being connected to a said selection transistor; controlling individual memory transistors with a plurality of word lines, each of which is connected to a gate electrode of one of said memory transistors; and controlling said selection transistors with a plurality of selection lines connected to gate electrodes of said selection transistors; precharging said sub bit lines with a program prohibit voltage; discharging only a selected sub bit line which placing all non-selected sub bit lines in a floating state; providing a programming voltage on a word line connected to a selected memory transistor connected to said selected sub bit line.
Claim 23
Independent Claim
166 words
A method of programming a nonvolatile memory device comprising: controlling connections between a main bit line and a plurality of sub bit lines with connection control transistors; controlling connections between a plurality of groups of memory transistors and each of sad sub bit lines with a selection transistor, wherein each said group of memory transistors comprises a plurality of memory transistors connected in series, said series being connected to a said selection transistor; controlling individual memory transistors with a plurality of word lines, each of which is connected to a gate electrode of one of said memory transistors; and controlling said selection transistors with a plurality of selection lines connected to gate electrodes of said selection transistors; precharging said sub bit lines with a program prohibit voltage; discharging only a selected sub bit line which placing all non-selected sub bit lines in a floating state; providing a programming voltage on a word line connected to a selected memory transistor connected to said selected sub bit line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-18 | 2003-04-19 | 2003-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-18 | 2007-04-19 | 2007-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-18 | 2011-04-19 | 2011-10-19 | $7700.00 | Window Closed / Lapsed |