Computer system having organization for multiple condition code setting and for testing instruction out-of-order

Claim 1

A computer system comprising: multiple functional units for executing instructions; issuing means for issuing instructions for processing by said functional units and including an instruction issue unit; a buffer; one or more register files; a cache store coupled between main memory and said functional units; an interconnection network coupling said functional units, said register files, and said instruction issue unit; means for concurrently executing multiple out-of-order instructions; means for attaching an I-Group comprising an instruction and a tag, a read-vector, a write vector, and a type vector as control bits for instructional use by the system for permitting the hardware of the system to schedule concurrently and on a short cycle time basis multiple, possibly out-of-order, instruction issuances to multiple functional units for execution and to transfer I-Groups to the buffer or for scheduling by said issue unit; an instruction scheduling mechanism and in which the issue unit includes assigning means for concurrently assigning and issuing independent, multiple, out-of-order instructions contained in the instruction scheduling mechanism provided by said issue unit to the multiple functional units for execution; and ports connecting the issue unit to the multiple functional units, wherein said assigning means includes prioritization means for prioritizing eligible instructions by the assignment to each port of a port-type through which an instruction of a matching instruction type, as specified in its I-Group, may be issued to a functional unit that is able to execute it so that independent instructions eligible for transfer may outnumber available functional units for paths via a port through which instructions may be transferred.