US5998807A
Expired / Lapsed
US
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Integrated CMOS circuit arrangement and method for the manufacture thereof
Assignee: Infineon Technologies AG
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Filing: 1997-09-09
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Granted: 1999-12-07
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Expires: 2017-09-09
Abstract
Abstract Semiconductor islands respectively comprise at least a Si 1-x Ge x layer and a distorted silicon layer that exhibits essentially the same lattice constant as the Si 1-x Ge x layer are formed on an insulating layer that is located on a carrier plate. The semiconductor islands are preferably formed by selective epitaxy and comprise p-channel MOS transistors and/or n-channel MOS transistors.
Inventors
- 👤 Bernhard Lustig
- 👤 Herbert Schaefer
- 👤 Martin Franosch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 12:08
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/01; H10D84/02; H10D86/00; H10D86/201
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
81 words
An integrated and symmetrical CMOS circuit comprising: a plurality of semiconductor islands formed above an insulating layer, the plurality of semiconductor islands respectively comprising at least a Si 1-x Ge x layer, a strained, non-distorted silicon layer that exhibits substantially a same lattice constant as the Si 1-x Ge x layer, and at least one MOS transistor wherein the gate electrodes of the MOS transistors contain polycrystalline germanium such that n-channel transistors and p-channel transistors have substantially the same threshold voltages.
Claim 2
Dependent Claim
81 words
An integrated and symmetrical CMOS circuit comprising: a plurality of semiconductor islands formed above an insulating layer, the plurality of semiconductor islands respectively comprising at least a Si 1-x Ge x layer, a strained, non-distorted silicon layer that exhibits substantially a same lattice constant as the Si 1-x Ge x layer, and at least one MOS transistor wherein the gate electrodes of the MOS transistors contain polycrystalline germanium such that n-channel transistors and p-channel transistors have substantially the same threshold voltages.
Claim 3
Dependent Claim
32 words
The CMOS circuit of claim 1, wherein a p-channel MOS transistor is provided in at least one semiconductor island and an n-channel MOS transistor is provided in at least one semiconductor island.
Claim 4
Dependent Claim
24 words
A CMOS circuit according to claim 1, wherein a silicon layer is formed between the Si 1-x Ge x layer and the insulating layer.
Claim 5
Dependent Claim
64 words
A CMOS circuit according to claim 3, wherein the structured silicon layer has a thickness of less than 20 nm; and the Si 1-x Ge x layer has a thickness of from 10 nm to 50 nm and a germanium composition of between 20 percent and 50 percent; and wherein the strained silicon layer has a thickness of between 5 nm and 20 nm.
Claim 6
Dependent Claim
38 words
A CMOS circuit according to claim 4, wherein a buffer layer that contains Si y-1 Ge y and in which the germanium content decreases is formed between the Si 1-x Ge x layer and the strained silicon layer.
Claim 7
Dependent Claim
25 words
A CMOS circuit according to claim 1, wherein at least one p-channel transistor and one n-channel transistor are formed in at least one semiconductor island.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-06 | 2003-06-07 | 2003-12-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-06 | 2007-06-07 | 2007-12-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-06 | 2011-06-07 | 2011-12-07 | $7700.00 | Window Closed / Lapsed |