US6009014A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Erase verify scheme for NAND flash
Assignee: Advanced Micro Devices Inc
•
Filing: 1998-06-03
•
Granted: 1999-12-28
•
Expires: 2018-06-03
Abstract
Abstract The present invention provides a method of verifying that all flash EEPROM transistors in a NAND string are properly erased without overerasing by applying a bias voltage to the source of the bottom select gate of the NAND array and applying a non-negative erase verify voltage to the control gates of each transistor during an erase verify. The bias voltage is at least equal to the erased threshold voltage of the worst case transistor to ensure proper erase verification. If all transistors are not erased, then another erase operation is performed. Erasing is repeated until the erase verify operation indicates that all transistors are properly erased. By erasing and verifying according to the present invention, the NAND array is completely and properly erased while minimizing overerasing the array.
Inventors
- 👤 Shane C. Hollmer
- 👤 Chung-You Hu
- 👤 Binh Q. Le
- 👤 Pau-Ling Chen
- 👤 Jonathan Su
- 👤 Ravi Gutala
- 👤 Colin Bill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 23:44
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/344; G11C16/3445; G11C16/04; G11C16/0483
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
102 words
A method of erase verifying for a NAND string, said string comprising a plurality of floating gate transistors coupled between a string-select transistor and a ground-select transistor, said method comprising: applying a first voltage to the select gate of the string-select transistor; applying a second voltage to the select gate of the ground-select transistor; applying a sensing current to the drain of the string-select transistor; applying a non-negative erase verify voltage to the control gate of the floating gate transistors; applying a bias voltage to the source of the ground-select transistor; and detecting whether the sensing current flows through the NAND string.
Claim 2
Independent Claim
102 words
A method of erase verifying for a NAND string, said string comprising a plurality of floating gate transistors coupled between a string-select transistor and a ground-select transistor, said method comprising: applying a first voltage to the select gate of the string-select transistor; applying a second voltage to the select gate of the ground-select transistor; applying a sensing current to the drain of the string-select transistor; applying a non-negative erase verify voltage to the control gate of the floating gate transistors; applying a bias voltage to the source of the ground-select transistor; and detecting whether the sensing current flows through the NAND string.
Claim 3
Dependent Claim
20 words
The method of claim 1, wherein said first and second voltages turn on said string-select and said ground-select transistors, respectively.
Claim 4
Dependent Claim
14 words
The method of claim 1, wherein said erase verify voltage is approximately 0 volts.
Claim 5
Dependent Claim
11 words
The method of claim 1, wherein said bias voltage is positive.
Claim 6
Dependent Claim
29 words
The method of claim 1, wherein said NAND string is properly erased when the sensing current is detected and not properly erased when the sensing current is not detected.
Claim 7
Dependent Claim
19 words
The method of claim 1, wherein the detecting detects whether the entire sensing current flows through the NAND string.
Claim 8
Dependent Claim
31 words
The method of claim 6, wherein said NAND string is properly erased when the entire sensing current is detected and not properly erased when the entire sensing current is not detected.
Claim 9
Dependent Claim
32 words
The method of claim 1, wherein said NAND string is properly erased when all the floating gate transistors have erased threshold voltages less than or equal to a desired erased threshold voltage.
Claim 10
Dependent Claim
32 words
The method of claim 8, wherein said desired erased threshold voltage is the erase verify voltage minus the bias voltage minus the amount of overdrive needed to sink the entire sensing current.
Claim 11
Independent Claim
148 words
A method of minimizing overerase of a NAND string, said string comprising a plurality of floating gate transistors coupled between a string-select transistor and a ground-select transistor, said method comprising: performing an erase operation on said NAND string; performing an erase verify operation on said NAND string, said erase verify operation comprising: applying a first voltage to the select gate of the string-select transistor; applying a second voltage to the select gate of the ground-select transistor; applying a sensing current to the drain of the string-select transistor; applying a non-negative erase verify voltage to the control gate of the floating gate transistors; applying a bias voltage to the source of the ground-select transistor; and detecting whether the sensing current flows through the NAND string; and if no current is detected, performing a series of erase operations followed by said erase verify operation until the sensing current is detected.
Claim 12
Independent Claim
148 words
A method of minimizing overerase of a NAND string, said string comprising a plurality of floating gate transistors coupled between a string-select transistor and a ground-select transistor, said method comprising: performing an erase operation on said NAND string; performing an erase verify operation on said NAND string, said erase verify operation comprising: applying a first voltage to the select gate of the string-select transistor; applying a second voltage to the select gate of the ground-select transistor; applying a sensing current to the drain of the string-select transistor; applying a non-negative erase verify voltage to the control gate of the floating gate transistors; applying a bias voltage to the source of the ground-select transistor; and detecting whether the sensing current flows through the NAND string; and if no current is detected, performing a series of erase operations followed by said erase verify operation until the sensing current is detected.
Claim 13
Dependent Claim
14 words
The method of claim 10, wherein said erase verify voltage is approximately 0 volts.
Claim 14
Dependent Claim
11 words
The method of claim 10, wherein said bias voltage is positive.
Claim 15
Dependent Claim
28 words
The method of claim 10, wherein said performing a series of erase operations followed by said erase verify operation is performed until the entire sensing current is detected.
Claim 16
Dependent Claim
32 words
The method of claim 10, wherein said NAND string is properly erased when all the floating gate transistors have erased threshold voltages less than or equal to a desired erased threshold voltage.
Claim 17
Dependent Claim
32 words
The method of claim 14, wherein said desired erased threshold voltage is the erase verify voltage minus the bias voltage minus the amount of overdrive needed to sink the entire sensing current.
References Cited (Backward Citations)
US5473563A
Cited
US5671178A
Cited
US5696717A
Cited
US5726934A
Cited
US5748538A
Cited
US5862074A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-27 | 2003-06-28 | 2003-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-27 | 2007-06-28 | 2007-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-27 | 2011-06-28 | 2011-12-28 | $7700.00 | Window Closed / Lapsed |