US6014330A
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Non-volatile semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1998-10-08
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Granted: 2000-01-11
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Expires: 2018-10-08
Abstract
Abstract A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.
Inventors
- 👤 Tetsuo Endoh
- 👤 Yoshiyuki Tanaka
- 👤 Seiichi Aritome
- 👤 Riichiro Shirota
- 👤 Susumu Shuto
- 👤 Tomoharu Tanaka
- 👤 Gertjan Hemink
- 👤 Toru Tanzawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 14:19
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0483; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5635; G11C16/06; G11C16/08; G11C16/10; G11C16/12; G11C16/14; G11C16/34; G11C16/3404; G11C16/3436; G11C16/344; G11C16/3445; G11C16/3454; G11C16/3459; G11C16/3468; G11C16/3477; G11C16/3486; G11C2211/00; G11C2211/56; G11C2211/562; G11C2211/5621
Claims Analysis
Total Claims: 61
Claim 1
Independent Claim
114 words
A method of programming to a predetermined state a memory cell connected in series with a plurality of nonvolatile memory cells to constitute a NAND-cell unit, comprising: applying a programming pulse to said plurality of memory cells, in which a predetermined number of said plurality of memory cells are connected in series to constitute a NAND-cell unit, so as to program said memory cell to said predetermined state, said programming pulse having a programming voltage gradually raised up; determining whether said memory cell has been successfully programmed to said predetermined state; and terminating application of said programming pulse to said memory cell if said memory cell has been successfully programmed to said predetermined state.
Claim 2
Independent Claim
114 words
A method of programming to a predetermined state a memory cell connected in series with a plurality of nonvolatile memory cells to constitute a NAND-cell unit, comprising: applying a programming pulse to said plurality of memory cells, in which a predetermined number of said plurality of memory cells are connected in series to constitute a NAND-cell unit, so as to program said memory cell to said predetermined state, said programming pulse having a programming voltage gradually raised up; determining whether said memory cell has been successfully programmed to said predetermined state; and terminating application of said programming pulse to said memory cell if said memory cell has been successfully programmed to said predetermined state.
Claim 3
Dependent Claim
13 words
The method of claim 1, wherein said programming pulse has a staircase shape.
Claim 4
Dependent Claim
13 words
The method of claim 1, wherein said programming pulse has a trapezoidal shape.
Claim 5
Dependent Claim
45 words
The method of claim 2 or 3, wherein said programming pulse is divided into a plurality of sub-pulses and wherein whether said memory cell has been successfully programmed is determined during a time when said plurality of sub-pulses is not applied to said memory cell.
Claim 6
Dependent Claim
33 words
The method of claim 4, wherein a first pulse of said plurality of sub-pulses has a first pulse duration and pulse durations of remaining subsequent sub-pulses are shorter than said first pulse duration.
Claim 7
Dependent Claim
29 words
The method of claim 5, wherein said first pulse duration of said first pulse is sufficient to cause programming of said memory cell to occur in a saturated region.
Claim 8
Dependent Claim
46 words
The method of claim 1, wherein each of said plurality of memory cells comprises a field effect transistor including a charge storage portion, said memory cell being coupled to a bitline at a drain electrode and being coupled to a word line at a gate electrode.
Claim 9
Dependent Claim
27 words
The method of claim 7, wherein said programming voltage is defined by a bitline voltage of said bitline and a word line voltage of said word line.
Claim 10
Dependent Claim
22 words
The method of claim 8, wherein said word line voltage is gradually raised up and said bitline voltage has a constant value.
Claim 11
Dependent Claim
16 words
The method of claim 9, wherein said word line voltage is limited by a predetermined voltage.
Claim 12
Dependent Claim
31 words
The method of claim 9, wherein the word line voltages of remaining memory cells in said NAND-cell unit are gradually raised up and are lower than a selected word line voltage.
Claim 13
Dependent Claim
21 words
The method of claim 8, wherein said word line voltage has a constant value and said bitline voltage is gradually decreased.
Claim 14
Dependent Claim
28 words
The method of claim 1, wherein said predetermined state is one of at least two states, and said memory cell stores one of said at least two states.
Claim 15
Dependent Claim
28 words
The method of claim 1, wherein said predetermined state is one of at least three states, and said memory cell stores one of said at least three states.
Claim 16
Dependent Claim
24 words
The method of claim 1, wherein said predetermined state is one of multi-level states, and said memory call stores one of said multi-level states.
Claim 17
Dependent Claim
26 words
The method of claim 15, wherein said programming voltage is determined by one of said multilevel states which is to be programmed into said memory cell.
Claim 18
Independent Claim
103 words
A method of programming a plurality of nonvolatile memory cells, which are connected in series to constitute NAND-cell units, to respective predetermined states, comprising: applying programming pulses simultaneously to respective of said memory cells so as to program said memory cells to said respective predetermined states, said programming pulses having respective programming voltages gradually raised up; determining which of given memory cells to which programming pulses have been applied have been successfully programmed to said respective predetermined states; and terminating cell-by-cell application of programming pulses to each of respective given memory cells determined to have been successfully programmed to said predetermined state cell-by-cell.
Claim 19
Independent Claim
103 words
A method of programming a plurality of nonvolatile memory cells, which are connected in series to constitute NAND-cell units, to respective predetermined states, comprising: applying programming pulses simultaneously to respective of said memory cells so as to program said memory cells to said respective predetermined states, said programming pulses having respective programming voltages gradually raised up; determining which of given memory cells to which programming pulses have been applied have been successfully programmed to said respective predetermined states; and terminating cell-by-cell application of programming pulses to each of respective given memory cells determined to have been successfully programmed to said predetermined state cell-by-cell.
Claim 20
Dependent Claim
13 words
The method of claim 13, wherein each programming pulse has a staircase shape.
Claim 21
Dependent Claim
13 words
The method of claim 17, wherein each programming pulse has a trapezoidal shape.
Claim 22
Independent Claim
52 words
The method of claims 17, 18 or 19, wherein said programming pulses are divided into a plurality of sub-pulses and wherein whether each of said given memory cells has been successfully programmed is determined during a time when said plurality of sub-pulses are not applied to each of said given memory cells.
Claim 23
Dependent Claim
31 words
The method of claim 20, wherein a first pulse of said sub-pulses has a first pulse duration and pulse durations of remaining subsequent sub-pulses are shorter than said first pulse duration.
Claim 24
Dependent Claim
29 words
The method of claim 21, wherein said first pulse duration of said first pulse is sufficient to cause programming of said memory cells to occur in a saturated region.
Claim 25
Dependent Claim
50 words
The method of claim 17, wherein each of said memory cells has a structure of a field effect transistor including a charge storage portion, and each of said memory cells is coupled to a bitline at a drain electrode and is coupled to a word line at a gate electrode.
Claim 26
Dependent Claim
30 words
The method of claim 23, wherein each of said programming voltages is defined by a bitline voltage of the respective bitline and a word line voltage of said word line.
Claim 27
Dependent Claim
22 words
The method of claim 24, wherein said word line voltage is gradually raised up and said bitline voltage has a constant value.
Claim 28
Dependent Claim
16 words
The method of claim 25, wherein said word line voltage is limited by a predetermined voltage.
Claim 29
Dependent Claim
31 words
The method of claim 25, wherein the word line voltages of remaining memory cells in said NAND-cell unit are gradually raised up and are lower than a selected word line voltage.
Claim 30
Dependent Claim
21 words
The method of claim 24, wherein said word line voltage has a constant value and said bitline voltage is gradually decreased.
Claim 31
Dependent Claim
32 words
The method of claim 17, wherein each of said predetermined states is one of at least two states, and each of said memory cells stores one of said at least two states.
Claim 32
Dependent Claim
32 words
The method of claim 17, wherein each of said predetermined states is one of at least three states, and each of said memory cells stores one of said at least three states.
Claim 33
Dependent Claim
28 words
The method of claim 17, wherein each of said predetermined states is one of multi-level states, and each of said memory cells stores one of said multi-level states.
Claim 34
Dependent Claim
25 words
The method of claim 31, wherein each programming voltage is determined by the predetermined state which is to be programmed into the corresponding memory cell.
Claim 35
Independent Claim
84 words
A method of erasing a memory cell connected in series with a plurality of non-volatile memory cells to constitute a NAND-cell unit, comprising: applying an erasing pulse to said memory cell so as to erase said memory cell, said erasing pulse having an erasing voltage gradually raised up; determining whether said memory cell has been successfully erased; and terminating application of said erasing pulse to said memory cell when it is determined that said memory cell has been successfully erased to a predetermined state.
Claim 36
Independent Claim
84 words
A method of erasing a memory cell connected in series with a plurality of non-volatile memory cells to constitute a NAND-cell unit, comprising: applying an erasing pulse to said memory cell so as to erase said memory cell, said erasing pulse having an erasing voltage gradually raised up; determining whether said memory cell has been successfully erased; and terminating application of said erasing pulse to said memory cell when it is determined that said memory cell has been successfully erased to a predetermined state.
Claim 37
Dependent Claim
13 words
The method of claim 33, wherein said erasing pulse has a staircase shape.
Claim 38
Dependent Claim
13 words
The method of claim 33, wherein said erasing pulse has a trapezoidal shape.
Claim 39
Independent Claim
45 words
The method of claims 33, 34 or 35, wherein said erasing pulse is divided into a plurality of sub-pulses and whether said memory cell has been successfully erased is determined during a time when said plurality of sub-pulses are not applied to said memory cell.
Claim 40
Dependent Claim
33 words
The method of claim 36, wherein a first pulse of said plurality of sub-pulses has a first pulse duration and pulse durations of remaining subsequent sub-pulses are shorter than said first pulse duration.
Claim 41
Dependent Claim
29 words
The method of claim 37, wherein said first pulse duration of said first pulse is sufficient to cause erasing of said memory cell to occur in a saturated state.
Claim 42
Independent Claim
93 words
A method of erasing a plurality of nonvolatile memory cells which are connected in series to constitute NAND-cell units, comprising: applying erasing pulses simultaneously to respective of said memory cells so as to erase said memory cells, said erasing pulses each having an erasing voltage gradually raised up; determining which of given memory cells to which erasing pulses have been applied have been successfully erased; and terminating cell-by-cell application of the erasing pulse to each respective given memory cell when it is determined that the respective given memory cell has been successfully erased.
Claim 43
Independent Claim
93 words
A method of erasing a plurality of nonvolatile memory cells which are connected in series to constitute NAND-cell units, comprising: applying erasing pulses simultaneously to respective of said memory cells so as to erase said memory cells, said erasing pulses each having an erasing voltage gradually raised up; determining which of given memory cells to which erasing pulses have been applied have been successfully erased; and terminating cell-by-cell application of the erasing pulse to each respective given memory cell when it is determined that the respective given memory cell has been successfully erased.
Claim 44
Dependent Claim
13 words
The method of claim 39, wherein each erasing pulse has a staircase shape.
Claim 45
Dependent Claim
13 words
The method of claim 39, wherein each erasing pulse has a trapezoidal shape.
Claim 46
Independent Claim
52 words
The method of claims 39, 40 or 41, wherein each of said erasing pulses is divided into a plurality of sub-pulses and wherein whether each of said memory cells has been erased is determined during a time when said plurality of sub-pulses is not applied to each of said given memory cells.
Claim 47
Dependent Claim
31 words
The method of claim 42, wherein a first pulse of said sub-pulses has a first pulse duration and pulse durations of remaining subsequent sub-pulses are shorter than said first pulse duration.
Claim 48
Dependent Claim
29 words
The method of claim 43, wherein said first pulse duration of said first pulse is sufficient to cause erasing of said memory cell to occur in a saturated region.
Claim 49
Dependent Claim
151 words
A non-volatile semiconductor memory device comprising: a semiconductor substrate; a plurality of bit lines; a plurality of word lines insulatively intersecting said bit lines; a memory cell array comprising a plurality of memory cells each including a transistor with a charge storage portion, said memory cells connected in series to constitute NAND-cell units coupled to said bit lines and said word lines, and a plurality of programming circuits coupled to said memory cell array, for storing control data which define whether or not programming pulses having respective programming voltages gradually raised up are to be applied to respective of said memory cells, for applying said programming pulses to respective of said memory cells according to the stored control data and for selectively modifying said stored control data in order to apply said programming pulses only to memory cells in which it has been determined that data has not been successfully programmed.
Claim 50
Dependent Claim
151 words
A non-volatile semiconductor memory device comprising: a semiconductor substrate; a plurality of bit lines; a plurality of word lines insulatively intersecting said bit lines; a memory cell array comprising a plurality of memory cells each including a transistor with a charge storage portion, said memory cells connected in series to constitute NAND-cell units coupled to said bit lines and said word lines, and a plurality of programming circuits coupled to said memory cell array, for storing control data which define whether or not programming pulses having respective programming voltages gradually raised up are to be applied to respective of said memory cells, for applying said programming pulses to respective of said memory cells according to the stored control data and for selectively modifying said stored control data in order to apply said programming pulses only to memory cells in which it has been determined that data has not been successfully programmed.
Claim 51
Dependent Claim
13 words
The device of claim 45, wherein said programming pulses have a staircase shape.
Claim 52
Dependent Claim
13 words
The device of claim 45, wherein said programming pulses have a trapezoidal shape.
Claim 53
Dependent Claim
67 words
The device of claim 45, 46 or 47, wherein each of said programming pulses is divided into a plurality of sub-pulses and wherein said actual programmed states of said memory cells are determined when said sub-pulses are not applied to said respective memory cells, and said stored control data are modified during a time when said sub-pulses are not applied to said respective of said memory cells.
Claim 54
Dependent Claim
31 words
The device of claim 48, wherein a first pulse of said sub-pulses has a first pulse duration and pulse durations of remaining subsequent sub-pulses are shorter than said first pulse duration.
Claim 55
Dependent Claim
29 words
The device of claim 49, wherein said first pulse duration of said first pulse is sufficient to cause programming of said memory cell to occur in a saturated state.
Claim 56
Dependent Claim
32 words
The device of claim 45, wherein said programming voltages are simultaneously applied to memory cells which are connected to respective said bit lines and commonly connected to one of said word lines.
Claim 57
Dependent Claim
30 words
The device of claim 51, wherein each programming voltage is defined by a bit line voltage of said respective bit lines and a word line voltage of said word line.
Claim 58
Dependent Claim
22 words
The device of claim 52, wherein said word line voltage is gradually raised up and said bitline voltage has a constant value.
Claim 59
Dependent Claim
17 words
The device or claim 53, wherein said word line voltage is limited by a predetermined maximum voltage.
Claim 60
Dependent Claim
49 words
The device of claim 53, wherein a selected memory cell to be programmed is included in said NAND-cell unit, and word line voltages of remaining unselected memory cells in said NAND-cell unit are lower than the word line voltage of the selected memory cell and are gradually raised up.
Claim 61
Dependent Claim
21 words
The device of claim 52, wherein said word line voltage has a constant value and each bitline voltage is gradually decreased.
References Cited (Backward Citations)
US5544117A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2003-01-10 | 2003-07-12 | 2004-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-10 | 2007-07-12 | 2008-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-10 | 2011-07-12 | 2012-01-11 | $7700.00 | Window Closed / Lapsed |