Output pad circuit using control signal

Claim 2

An output pad circuit includes a first and second transistors coupled in series between a first potential and a second potential, wherein respective control electrodes of the first and second transistors receive an inverted input data signal, the output pad circuit further comprising: an output node coupled to the first and second transistors to transmit an output signal; and a tri-state inverter coupled to the output node that receives a control signal and the input data signal, wherein when the output pad circuit is at steady state, a driving current of the output signal is selectable from at least three different values based on the input signal and the control signal, and wherein the output node is coupled to an external load, and the coupled external load is one of a plurality of prescribed load values, and the driving current of the output signal is selected from the at least three different values based on the coupled external load using the input and control signals.

Claim 3

The output pad circuit of claim 1, wherein the tri-state inverter comprises: an inverter; third through sixth third through sixth transistors coupled in series between the first potential and the second potential, wherein control electrodes of the third transistor and the sixth transistor receive different levels of the control signal, wherein respective control electrodes of the fourth transistor and the fifth transistor receive the inverted input data signal; and an output terminal between the fourth transistor and the fifth transistor is coupled to an output terminal of the output pad circuit, wherein the first and second transistors are directly connected between a supply voltage and a ground voltage, and wherein the output node is coupled to the output terminal.

Claim 4

The output pad circuit of claim 1, wherein the tri-state inverter operates as an inverter when the control signal is a high level, and wherein an output signal of the tri-state inverter is a tri-state level when the control signal is a low level.

Claim 5

The output pad circuit of claim 1, wherein the tri-state inverter comprises: a first logic gate for logically processing the input data signal and the control signal; a second logic gate for logically processing the inverted input data signal and the control signal; and third and fourth transistors coupled in series between the first potential and the second potential, and wherein control electrodes of the third and fourth transistors respectively receive an output value of the first logic gate and an output value of the second logic gate, wherein the first and second transistors are directly connected between a supply voltage and a ground voltage.

Claim 6

The output pad circuit of claim 1, wherein the first transistor is a PMOS transistor, the second transistor is an NMOS transistor, the first and second potentials are respectively a supply voltage and a ground voltage, and wherein the control electrode is a gate.

Claim 7

The output pad circuit of claim 1, wherein the driving current value of the output signal when the control signal is the high level is two times (2x) the driving current value when the control signal is the low level.

Claim 8

The output pad circuit of claim 1, wherein the output node coupled to a load, wherein the load is selectable between a high load and a low load, and wherein the driving current of the output signal is determined according to the selected load.

Claim 9

An internal control circuit for use with an output pad circuit that receives an input signal and outputs an output signal, the control circuit comprising a logic circuit that receives a control signal, wherein when the output pad circuit is at steady state, a driving current of the output signal of the output pad circuit is selectable from more than two different values based on the control signal applied to said internal control circuit, and wherein the logic circuit comprises a tri-state inverter that receives the control signal, wherein when the control signal is a prescribed level, the output value of the internal control circuit is a tri-state level, and wherein the tri-state inverter comprises: a first logic gate for logically processing the input signal and the control signal; a second logic gate for logically processing an inverted input data signal and the control signal; and third and fourth transistors coupled in series between a first potential and a second potential, and wherein control electrodes of the third and fourth transistors respectively receive an output value of the first logic gate and an output value of the second logic gate, wherein the first and second transistors are directly connected between a supply voltage and a ground voltage.

Claim 10

An internal control circuit for use with an output pad circuit that receives an input signal and outputs an output signal, the control circuit comprising a logic circuit that receives a control signal, wherein when the output pad circuit is at steady state, a driving current of the output signal of the output pad circuit is selectable from more than two different values based on the control signal applied to said internal control circuit, and wherein the logic circuit comprises a tri-state inverter that receives the control signal, wherein when the control signal is a prescribed level, the output value of the internal control circuit is a tri-state level, and wherein the tri-state inverter comprises: a first logic gate for logically processing the input signal and the control signal; a second logic gate for logically processing an inverted input data signal and the control signal; and third and fourth transistors coupled in series between a first potential and a second potential, and wherein control electrodes of the third and fourth transistors respectively receive an output value of the first logic gate and an output value of the second logic gate, wherein the first and second transistors are directly connected between a supply voltage and a ground voltage.

Claim 11

The internal control circuit of claim 8, wherein the tri-state inverter operates as an inverter when the control signal is a high level.

Claim 12

The internal control circuit of claim 8, wherein the first and second logic gates are respectively a NAND gate and an AND gate.

Claim 13

The internal control circuit of claim 8, wherein the selected value of the driving current when the control signal is a high level is two times (2x) a corresponding value of the driving current of the output signal when the control signal is a low level.

Claim 14

The internal control circuit of claim 8, further comprising: an input terminal that receives the input signal; two series coupled inverters that generate the output signal; and an output terminal that outputs the output signal.

Claim 15

A semiconductor device, comprising: an output pad circuit responsive to an input signal at an input electrode to provide an output signal at an output pad; a load coupled to the output pad circuit; and a control circuit coupled to said output pad circuit and responsive to a control signal such that a driving current of the output signal when the output pad circuit is at steady state is selectable from more than two different values based on the input signal and the control signal, wherein said output pad circuit includes first and second transistors directly connected in series between a supply voltage and a ground voltage and responsive to the input signal applied at the input electrode, said first and second transistors coupled to an output electrode of the output pad circuit at a common serial connection and having first and second channel length/width ratios.

Claim 16

A semiconductor device, comprising: an output pad circuit responsive to an input signal at an input electrode to provide an output signal at an output pad; a load coupled to the output pad circuit; and a control circuit coupled to said output pad circuit and responsive to a control signal such that a driving current of the output signal when the output pad circuit is at steady state is selectable from more than two different values based on the input signal and the control signal, wherein said output pad circuit includes first and second transistors directly connected in series between a supply voltage and a ground voltage and responsive to the input signal applied at the input electrode, said first and second transistors coupled to an output electrode of the output pad circuit at a common serial connection and having first and second channel length/width ratios.

Claim 17

The semiconductor device of claim 13, wherein said output pad circuit comprises: a first inverter coupled to the input electrode; and a second inverter coupled to said first inverter and the output electrode, wherein the second inverter comprises the first and second transistors.

Claim 18

The semiconductor device of claim 14, wherein said control circuit comprises a tri-state inverter coupled to an output of said first inverter and an output of said second inverter and responsive to the control and input signals, wherein the load has one of a plurality of different prescribed load values, and wherein the selected value of the driving current is based on a corresponding one of the different prescribed load values.

Claim 19

The semiconductor device of claim 13, wherein said control circuit comprises a plurality of serially connected transistors responsive to the input signal and the control signal to select the driving current value of the output signal at the output electrode.

Claim 20

The semiconductor device of claim 13, wherein the driving current value of the output signal is selectable from four different output values based on the input signal and the control signal.

Claim 21

The semiconductor device of claim 13, wherein said output pad circuit further comprises an inverter coupled to the input electrode, each of said first and second transistors having first, second and control electrodes, said second electrodes of said first and second transistors being coupled to each other to form the common serial connection and said first electrodes of said first and second transistors being coupled for receiving first and second voltages, respectively, wherein control electrodes of said first and second transistors are commonly coupled to receive an output of said inverter.

Claim 22

The semiconductor device of claim 16, wherein said output pad circuit further comprises a first inverter coupled to the input electrode and said first and second transistors; and said serially connected transistors of said control circuit comprise third, fourth, fifth and sixth transistors of third, fourth, fifth and sixth channel length/width ratios sequentially coupled in series, each having first, second and control electrodes, the control electrodes of said fourth and fifth transistors being coupled to an output of said first inverter and the second electrodes of said fourth and fifth transistor being coupled to the output electrode, said third and sixth transistors being responsive to the control signal.

Claim 23

The semiconductor device of claim 19, wherein said control circuit further comprises a second inverter coupled to receive the control signal and an output of said second inverter being coupled to the control electrode of said third transistor and the control electrode of said sixth transistor coupled to receive the control signal.

Claim 24

The semiconductor device of claim 16, wherein said output pad circuit further comprises a first inverter coupled to the input electrode and said first and second transistors; and said control circuit includes first and second logic units, each coupled for receiving the control signal, said first logic unit receiving the input signal and said second logic unit receiving an output of said first inverter, wherein said serially connected transistors of said control circuit comprises third and fourth transistors of third and fourth channel length/width ratios, each having first, second and control electrodes, the second electrodes of said third and fourth transistors being coupled to the output electrode, said control electrode of said third transistor being coupled to receive an output of said first logic unit and said control electrode of said fourth transistor being coupled for receiving an output of said second logic unit.

Claim 25

The semiconductor device of claim 20, wherein each of said third and fourth channel length/width ratios is greater than said first channel length/width ratio, and each of said fifth and sixth channel length/width ratios is greater than said second channel length/width ratio.

Claim 26

The semiconductor device of claim 21, wherein said third and fourth channel length/width ratios are greater than said first and second channel length/width ratios, respectively.

Claim 27

A circuit, comprising: an output pad circuit responsive to an input signal at an input electrode to provide an output signal at an output terminal; a load coupled to the output terminal; and a control circuit coupled to said output terminal and responsive to a control signal such that a driving current of the output signal when the circuit is at steady state is selectable from more than two different values based on the input signal and the control signal, wherein the load has one of a plurality of different prescribed load values, and wherein the selected value of the driving current is based on a corresponding one of the different prescribed load values the input signal and the control signal.

Claim 28

A circuit, comprising: an output pad circuit responsive to an input signal at an input electrode to provide an output signal at an output terminal; a load coupled to the output terminal; and a control circuit coupled to said output terminal and responsive to a control signal such that a driving current of the output signal when the circuit is at steady state is selectable from more than two different values based on the input signal and the control signal, wherein the load has one of a plurality of different prescribed load values, and wherein the selected value of the driving current is based on a corresponding one of the different prescribed load values the input signal and the control signal.

Claim 29

The circuit of claim 24, wherein the control circuit includes a tri-state inverter that comprises: a first logic gate for logically processing the input signal and the control signal; a second logic gate for logically processing the inverted input signal and the control signal; and third and fourth transistors coupled in series between the first potential and the second potential, and wherein control electrodes of the third and fourth transistors respectively receive an output value of the first logic gate and an output value of the second logic gate.

Claim 30

The circuit of claim 24, wherein said output pad circuit comprises: a first inverter coupled to the input electrode; and a second inverter coupled to said first inverter and the output electrode, and wherein said second inverter comprises first and second transistors directly connected in series between a first potential and second potential, wherein respective control electrodes of the first and second transistors receive the input signal.