US6058060A
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US
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Multi-bit-per-cell and analog/multi-level non-volatile memories with improved resolution and signal-to noise ratio
Assignee: SanDisk Technologies LLC
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Filing: 1998-12-31
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Granted: 2000-05-02
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Expires: 2018-12-31
Abstract
Abstract Applying a negative voltage to unselected word-lines during a read or verify operation reduces leakage current from over-erased memory cells, which allows the memory cells to be over-erased and therefore, to be programmed with lower threshold voltages. The consequence is a non-volatile memory having wider threshold voltage windows, which results in improved resolution and SNR for analog/multi-level and multi-bit-per-cell storage. During programming, the negative voltage is applied to word-lines containing unselected and erased memory cells in the same bit-line as the selected cell to prevent leakage current from over-erased cells, and a ground potential is applied to word-lines containing unselected and previously programmed cells in the selected bit-line to prevent drain disturb. In another embodiment, ground potential is applied to all the unselected word-lines during programming, which requires a programming load line and charge pump able to handle large currents and supply large voltages, respectively, due to the increased combined leakage current on the bit-line.
Inventors
- 👤 Sau C. Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 08:45
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/005; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5635; G11C11/5642; G11C16/00; G11C16/02; G11C16/06; G11C16/08; G11C16/30; G11C16/34; G11C16/3418; G11C8/00; G11C8/14
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
158 words
A method for operating a selected memory cell in an array of memory cells, comprising: during a read operation, applying a first negative voltage to a first word-line in the array, wherein the first word-line is not coupled to the selected memory cell; and applying a read voltage to a second word-line in the array, wherein the second word-line is coupled to the selected memory cell; and during a programming operation, applying the first negative voltage to a third word-line, wherein the third word-line is not coupled to the memory cell selected for programming and is coupled to memory cells in an erased state; applying a non-negative voltage to a fourth word-line, wherein the fourth word-line is not coupled to the memory cell selected for programming and is coupled to memory cells in a programmed state; and applying a programming voltage to a fifth word-line, wherein the fifth word-line is coupled to the memory cell selected for programming.
Claim 2
Independent Claim
158 words
A method for operating a selected memory cell in an array of memory cells, comprising: during a read operation, applying a first negative voltage to a first word-line in the array, wherein the first word-line is not coupled to the selected memory cell; and applying a read voltage to a second word-line in the array, wherein the second word-line is coupled to the selected memory cell; and during a programming operation, applying the first negative voltage to a third word-line, wherein the third word-line is not coupled to the memory cell selected for programming and is coupled to memory cells in an erased state; applying a non-negative voltage to a fourth word-line, wherein the fourth word-line is not coupled to the memory cell selected for programming and is coupled to memory cells in a programmed state; and applying a programming voltage to a fifth word-line, wherein the fifth word-line is coupled to the memory cell selected for programming.
Claim 3
Dependent Claim
13 words
The method of claim 1, wherein the non-negative voltage is approximately 0 volt.
Claim 4
Dependent Claim
14 words
The method of claim 1, wherein the first negative voltage is approximately -3 volts.
Claim 5
Independent Claim
107 words
A method for operating a selected memory cell in an array of memory cells, comprising: during a read operation, applying a first negative voltage to a first word-line in the array, wherein the first word-line is not coupled to the selected memory cell; and applying a read voltage to a second word-line in the array, wherein the second word-line is coupled to the selected memory cell; and during an erase operation, applying a second negative voltage to a third word-line, wherein the third word-line is coupled to memory cells to be erased, wherein the erasing operation over-erases some of the memory cells coupled to the third word-line.
Claim 6
Independent Claim
107 words
A method for operating a selected memory cell in an array of memory cells, comprising: during a read operation, applying a first negative voltage to a first word-line in the array, wherein the first word-line is not coupled to the selected memory cell; and applying a read voltage to a second word-line in the array, wherein the second word-line is coupled to the selected memory cell; and during an erase operation, applying a second negative voltage to a third word-line, wherein the third word-line is coupled to memory cells to be erased, wherein the erasing operation over-erases some of the memory cells coupled to the third word-line.
Claim 7
Dependent Claim
18 words
The method of claim 4, wherein the over-erased memory cells have threshold voltages less than approximately -1 volt.
Claim 8
Dependent Claim
20 words
The method of claim 5, wherein the over-erased memory cells have threshold voltages between approximately -2 volts and -1 volt.
Claim 9
Independent Claim
118 words
A method for operating a selected memory cell in an array of memory cells, comprising: during a read operation, applying a first negative voltage to a first word-line in the array, wherein the first word-line is not coupled to the selected memory cell; and applying a read voltage to a second word-line in the array, wherein the second word-line is coupled to the selected memory cell; and during a verify operation, applying a third negative voltage to a second word-line in the array, wherein the second word-line is not coupled to the selected memory cell; and applying a verify voltage to a fourth word-line in the array, wherein the fourth word-line is coupled to the selected memory cell.
Claim 10
Independent Claim
118 words
A method for operating a selected memory cell in an array of memory cells, comprising: during a read operation, applying a first negative voltage to a first word-line in the array, wherein the first word-line is not coupled to the selected memory cell; and applying a read voltage to a second word-line in the array, wherein the second word-line is coupled to the selected memory cell; and during a verify operation, applying a third negative voltage to a second word-line in the array, wherein the second word-line is not coupled to the selected memory cell; and applying a verify voltage to a fourth word-line in the array, wherein the fourth word-line is coupled to the selected memory cell.
Claim 11
Dependent Claim
15 words
The method of claim 7, wherein the first and third negative voltages are approximately equal.
Claim 12
Independent Claim
100 words
A method for programming a selected memory cell in an array of memory cells, comprising: applying a first negative voltage to a first word-line, wherein the first word-line is not coupled to the memory cell selected for programming and is coupled to memory cells in erased states; applying a non-negative voltage to a second word-line, wherein the second word-line is not coupled to the memory cell selected for programming and is coupled to memory cells in programmed states; and applying a programming voltage to a third word-line, wherein the third word-line is coupled to the memory cell selected for programming.
Claim 13
Independent Claim
100 words
A method for programming a selected memory cell in an array of memory cells, comprising: applying a first negative voltage to a first word-line, wherein the first word-line is not coupled to the memory cell selected for programming and is coupled to memory cells in erased states; applying a non-negative voltage to a second word-line, wherein the second word-line is not coupled to the memory cell selected for programming and is coupled to memory cells in programmed states; and applying a programming voltage to a third word-line, wherein the third word-line is coupled to the memory cell selected for programming.
Claim 14
Dependent Claim
29 words
The method of claim 9, wherein the programming voltage is between approximately 6 volts and 12 volts to program threshold voltages between approximately 0 volt and 6 volts, respectively.
Claim 15
Dependent Claim
58 words
The method of claim 9, further comprising: during a verify operation, applying a second negative voltage to a fourth word-line in the array, wherein the fourth word-line is not coupled to the selected memory cell; and applying a verify voltage to a fifth word-line in the array, wherein the fifth word-line is coupled to the selected memory cell.
Claim 16
Dependent Claim
13 words
The method of claim 9, wherein the non-negative voltage is approximately 0 volt.
Claim 17
Dependent Claim
14 words
The method of claim 9, wherein the first negative voltage is approximately -3 volts.
Claim 18
Independent Claim
145 words
A method for operating a selected memory cell in an array of memory cells, comprising: during a read operation, applying a first negative voltage to a first word-line in the array, wherein the first word-line is not coupled to the memory cell selected for reading; and applying a read voltage to a second word-line in the array, wherein the second word-line is coupled to the memory cell selected for reading; and during a programming operation, applying approximately 0 volt to a third word-line, wherein the third word-line is not coupled to the memory cell selected for programming; and applying a programming voltage to a fourth word-line, wherein the fourth word-line is coupled to the memory cell selected for programming, and wherein the programming voltage ranges from approximately 6 volts to 12 volts corresponding to threshold voltages ranging from approximately 0 volt to 6 volts, respectively.
Claim 19
Independent Claim
145 words
A method for operating a selected memory cell in an array of memory cells, comprising: during a read operation, applying a first negative voltage to a first word-line in the array, wherein the first word-line is not coupled to the memory cell selected for reading; and applying a read voltage to a second word-line in the array, wherein the second word-line is coupled to the memory cell selected for reading; and during a programming operation, applying approximately 0 volt to a third word-line, wherein the third word-line is not coupled to the memory cell selected for programming; and applying a programming voltage to a fourth word-line, wherein the fourth word-line is coupled to the memory cell selected for programming, and wherein the programming voltage ranges from approximately 6 volts to 12 volts corresponding to threshold voltages ranging from approximately 0 volt to 6 volts, respectively.
Claim 20
Dependent Claim
62 words
The method of claim 14, further comprising: during a verify operation, applying a second negative voltage to a fifth word-line in the array, wherein the fifth word-line is not coupled to the memory cell selected for verifying; and applying a verify voltage to a sixth word-line in the array, wherein the sixth word-line is coupled to the memory cell selected for verifying.
Claim 21
Dependent Claim
31 words
The method of claim 14, wherein the programming voltage ranges from approximately 6 volts to 12 volts corresponding to the verify voltage ranging from approximately 0 volt to 6 volts, respectively.
Claim 22
Dependent Claim
92 words
A non-volatile memory, comprising: an array of memory cells, the array including a set of word-lines, wherein each word-line is coupled to control gates of memory cells in a row associated with the word-line; and a word-line decoder coupled to the array, wherein the word-line decoder applies to a first word-line in the array, wherein the first word-line is not coupled to the selected memory cell, a negative voltage during a read or verify operation of the selected memory cell, or approximately 0 volt during a programming operation of the selected cell.
Claim 23
Dependent Claim
92 words
A non-volatile memory, comprising: an array of memory cells, the array including a set of word-lines, wherein each word-line is coupled to control gates of memory cells in a row associated with the word-line; and a word-line decoder coupled to the array, wherein the word-line decoder applies to a first word-line in the array, wherein the first word-line is not coupled to the selected memory cell, a negative voltage during a read or verify operation of the selected memory cell, or approximately 0 volt during a programming operation of the selected cell.
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 2003-05-02 | 2003-11-01 | 2004-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-02 | 2007-11-01 | 2008-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-02 | 2011-11-01 | 2012-05-02 | $7700.00 | Window Closed / Lapsed |