US6058066A — Enhanced register array accessible by both a syst…

Claim 1

Independent Claim 111 words

A register array, comprising: (a) a random access memory (RAM) including a plurality of status bits each of which is configured to store a value indicating whether particular data values stored in said RAM are active, wherein said status bits are configured to allow said value to be read without having to read said particular data values; (b) timing circuitry configured to control a timing of said register array operations; (c) row select circuitry configured to select a row in said RAM; (d) column select circuitry configured to select a column in said RAM; and (e) a status line, coupled to said plurality of status bits, configured to read said values.

Claim 2

Dependent Claim 111 words

A register array, comprising: (a) a random access memory (RAM) including a plurality of status bits each of which is configured to store a value indicating whether particular data values stored in said RAM are active, wherein said status bits are configured to allow said value to be read without having to read said particular data values; (b) timing circuitry configured to control a timing of said register array operations; (c) row select circuitry configured to select a row in said RAM; (d) column select circuitry configured to select a column in said RAM; and (e) a status line, coupled to said plurality of status bits, configured to read said values.

Claim 3

Dependent Claim 20 words

The register array of claim 1, wherein said plurality of status bits are positioned on an edge of said RAM.

Claim 4

Dependent Claim 184 words

A register array suitable for a digital signal processor, comprising: (a) a random access memory (RAM) having a first and a second port; (b) a digital signal processor input/output port coupled to said first port and having a processor interface configured to be coupled to a digital signal processor; (c) a RAM input/output port coupled to said second port; (d) a register data port coupled to said RAM input/output port and having a register data bus interface configured to be coupled to a register data bus; (e) timing circuitry coupled to said RAM and configured to control timing of operations of said register array; (f) row select circuitry coupled to said RAM and configured to select a row in said RAM; (g) column select circuitry coupled to said RAM and configured to select a column in said RAM; and (h) an input/output channel ready signal line coupled to said timing circuitry, wherein said input/output channel ready signal line carries an input/output channel ready signal generated by said timing circuitry, and said input/output channel ready signal controls access to said digital signal processor input/output port.

Claim 5

Dependent Claim 184 words

A register array suitable for a digital signal processor, comprising: (a) a random access memory (RAM) having a first and a second port; (b) a digital signal processor input/output port coupled to said first port and having a processor interface configured to be coupled to a digital signal processor; (c) a RAM input/output port coupled to said second port; (d) a register data port coupled to said RAM input/output port and having a register data bus interface configured to be coupled to a register data bus; (e) timing circuitry coupled to said RAM and configured to control timing of operations of said register array; (f) row select circuitry coupled to said RAM and configured to select a row in said RAM; (g) column select circuitry coupled to said RAM and configured to select a column in said RAM; and (h) an input/output channel ready signal line coupled to said timing circuitry, wherein said input/output channel ready signal line carries an input/output channel ready signal generated by said timing circuitry, and said input/output channel ready signal controls access to said digital signal processor input/output port.

Claim 6

Dependent Claim 77 words

The register array of claim 3, further comprising: a row comparator coupled to said processor interface and said register data bus interface, and configured to compare a first number representing a row in said RAM to be accessed through said second port with a second number representing a row in said RAM to be accessed by said first port, and to send a signal to said timing circuitry if said first and said second numbers are equal.

Claim 7

Dependent Claim 32 words

The register array of claim 4 wherein said signal sent to said timing circuitry gates an output of said timing circuitry to inhibit a write to said RAM via said second port.

Claim 8

Dependent Claim 54 words

The register array of claim 3, wherein said RAM further comprises a plurality of status bits each of which stores a value indicating whether particular data values stored in said RAM are active, wherein said status bits are configured to allow said value to be read without having to read said particular data values.

Claim 9

Dependent Claim 22 words

The register array of claim 6, further comprising a status line, coupled to said plurality of status bits, for reading said values.

Claim 10

Dependent Claim 30 words

The register array of claim 3, wherein said column select circuitry includes incrementing circuitry for automatically incrementing the column selected whenever additional data is written to said register data port.

Claim 11

Dependent Claim 59 words

A register array, comprising: (a) a random access memory (RAM) including means for indicating whether a row in said RAM is active without requiring said row in said RAM to be read; (b) means for timing said register array operations; (c) means for selecting a row in said RAM; and (d) means for selecting a column in said RAM.

Claim 12

Dependent Claim 59 words

A register array, comprising: (a) a random access memory (RAM) including means for indicating whether a row in said RAM is active without requiring said row in said RAM to be read; (b) means for timing said register array operations; (c) means for selecting a row in said RAM; and (d) means for selecting a column in said RAM.

Claim 13

Dependent Claim 29 words

The register array of claim 9, wherein said means for selecting a column includes means for automatically incrementing the column selected whenever additional data is written to said RAM.

Claim 14

Dependent Claim 157 words

A register array suitable for a digital signal processor, comprising: (a) a random access memory (RAM) having a first and second port; (b) a digital signal processor input/output port coupled to said first port and having a processor interface configured to be coupled to a digital signal processor; (c) a RAM input/output port coupled to said second port; (d) a register data port coupled to said RAM input/output port and having a register data bus interface configured to be coupled to a register data bus; (e) means for timing said register array operations; (f) means for selecting a row in said RAM; (g) means for selecting a column in said RAM; and (h) an input/output channel ready signal line coupled to said timing circuitry, wherein said input/output channel ready signal line carries an input/output channel ready signal generated by said timing means, and said input/output channel ready signal controls access to said digital signal processor input/output port.

Claim 15

Dependent Claim 157 words

A register array suitable for a digital signal processor, comprising: (a) a random access memory (RAM) having a first and second port; (b) a digital signal processor input/output port coupled to said first port and having a processor interface configured to be coupled to a digital signal processor; (c) a RAM input/output port coupled to said second port; (d) a register data port coupled to said RAM input/output port and having a register data bus interface configured to be coupled to a register data bus; (e) means for timing said register array operations; (f) means for selecting a row in said RAM; (g) means for selecting a column in said RAM; and (h) an input/output channel ready signal line coupled to said timing circuitry, wherein said input/output channel ready signal line carries an input/output channel ready signal generated by said timing means, and said input/output channel ready signal controls access to said digital signal processor input/output port.

Claim 16

Dependent Claim 31 words

The register array of claim 11, wherein said means for selecting a column includes means for automatically incrementing the column selected whenever additional data is written to said register data port.

Claim 17

Dependent Claim 152 words

A register array suitable for a digital signal processor, comprising: (a) a random access memory (RAM) having a first and a second port, and comprising a plurality of status bits each of which stores a value indicating whether particular data values stored in said RAM are active, wherein said status bits are configured to allow said value to be read without having to read said particular data values; (b) a digital signal processor input/output port coupled to said first port and having a processor interface configured to be coupled to a digital signal processor; (c) a RAM input/output port coupled to said second port and having a register data bus interface configured to be coupled to a register data bus; (d) timing circuitry for timing said register array operations; (e) row select circuitry for selecting a row in said RAM; and (f) column select circuitry for selecting a column in said RAM.

Claim 18

Dependent Claim 152 words

A register array suitable for a digital signal processor, comprising: (a) a random access memory (RAM) having a first and a second port, and comprising a plurality of status bits each of which stores a value indicating whether particular data values stored in said RAM are active, wherein said status bits are configured to allow said value to be read without having to read said particular data values; (b) a digital signal processor input/output port coupled to said first port and having a processor interface configured to be coupled to a digital signal processor; (c) a RAM input/output port coupled to said second port and having a register data bus interface configured to be coupled to a register data bus; (d) timing circuitry for timing said register array operations; (e) row select circuitry for selecting a row in said RAM; and (f) column select circuitry for selecting a column in said RAM.

Claim 19

Dependent Claim 23 words

The register array of claim 13, further comprising a status line, coupled to said plurality of status bits, for reading said bit values.

Claim 20

Dependent Claim 77 words

The register array of claim 13, further comprising: a row comparator coupled to said processor interface and said register data bus interface, and configured to compare a first number representing a row in said RAM to be accessed through said second port with a second number representing a row in said RAM to be accessed by said first port, and to send a signal to said timing circuitry if said first and said second numbers are equal.

Claim 21

Dependent Claim 28 words

The register array of claim 13, wherein said column select circuitry includes incrementing circuitry for automatically incrementing the column selected whenever additional data is written to said RAM.

Claim 22

Dependent Claim 64 words

The register array of claim 13, wherein said timing circuitry includes: core timing circuitry for timing said digital signal processor input/output port operations; and input/output timing circuitry for timing said RAM input/output operations; wherein during a non-idle period of the RAM, said core timing circuitry provides a gating signal to said input/output timing circuitry to inhibit access to said RAM via said second port.

Claim 23

Dependent Claim 28 words

The register array of claim 17, wherein said core timing circuitry provides said gating signal during a period of data access of said RAM via said first port.

Claim 24

Dependent Claim 59 words

The register array of claim 17, further comprising a row comparator for comparing a number of a row in said RAM to be accessed through said second port with a number of a row in said RAM to be accessed by said first port, and sending a gating signal to said input/output timing circuitry when said numbers are equal.

Claim 25

Dependent Claim 161 words

A register array accessible by both a computer system microprocessor and a digital signal processor comprising: (a) a dual port random access memory (RAM) having a first port and a second port; (b) a digital signal processor input/output port coupled to said first port and having a processor interface configured to be coupled to a digital signal processor; (c) a RAM input/output coupled to said second port; (d) a register data port coupled to said RAM input/output port and having a register data bus interface configured to be coupled to a register data bus, the register array accessible by the computer system microprocessor via said register data bus; (e) timing circuitry for timing said register array operations, wherein said timing circuitry is configured to inhibit simultaneous access to said RAM via said first port and said second port; (f) row select circuitry for selecting a row in said RAM; and (g) column select circuitry for selecting a column in said RAM.

Claim 26

Dependent Claim 161 words

A register array accessible by both a computer system microprocessor and a digital signal processor comprising: (a) a dual port random access memory (RAM) having a first port and a second port; (b) a digital signal processor input/output port coupled to said first port and having a processor interface configured to be coupled to a digital signal processor; (c) a RAM input/output coupled to said second port; (d) a register data port coupled to said RAM input/output port and having a register data bus interface configured to be coupled to a register data bus, the register array accessible by the computer system microprocessor via said register data bus; (e) timing circuitry for timing said register array operations, wherein said timing circuitry is configured to inhibit simultaneous access to said RAM via said first port and said second port; (f) row select circuitry for selecting a row in said RAM; and (g) column select circuitry for selecting a column in said RAM.

Claim 27

Dependent Claim 19 words

The register array of claim 20, further comprising an input/output channel ready signal line coupled to said timing circuitry.

Claim 28

Dependent Claim 65 words

The register array of claim 20 wherein: said timing circuitry includes: core timing circuitry for timing said digital signal processor input/output port operations; and input/output timing circuitry for timing said RAM input/output port operations; wherein during a non-idle period of the RAM, said core timing circuitry provides a gating signal to said input/output timing circuitry to inhibit access to said RAM via the second port.

Claim 29

Dependent Claim 28 words

The register array of claim 22 wherein said core timing circuitry provides said gating signal during a period of data access of the RAM via said first port.

Claim 30

Dependent Claim 28 words

The register array of claim 22, wherein said column select circuitry includes incrementing circuitry for automatically incrementing the column selected whenever additional data is written to said RAM.

Claim 31

Dependent Claim 77 words

The register array of claim 22, further comprising: a row comparator coupled to said processor interface and said register data bus interface, and configured to compare a first number representing a row in said RAM to be accessed through said second port with a second number representing a row in said RAM to be accessed by said first port, and to send a signal to said timing circuitry if said first and said second numbers are equal.

Claim 32

Independent Claim 161 words

A method of using a register array, which is accessible by both a microprocessor of a host computer and a digital signal processor, to control accesses by said microprocessor and said digital signal processor of a random access memory (RAM) contained in said register array, wherein said RAM comprises rows and columns, comprising: (a) providing a RAM idle condition; (b) detecting attempts by said microprocessor to access a row in said RAM currently subject to accesses by said digital signal processor; (c) disabling said microprocessor from accessing said RAM either when said RAM is not in said idle condition or when said microprocessor is attempting to access a row in said RAM currently subject to accesses by said digital signal processor; and (d) enabling said microprocessor to access said RAM when said register array is in said idle condition and said microprocessor is not attempting to access a row in said RAM currently subject to accesses by said digital signal processor.

Claim 33

Independent Claim 161 words

A method of using a register array, which is accessible by both a microprocessor of a host computer and a digital signal processor, to control accesses by said microprocessor and said digital signal processor of a random access memory (RAM) contained in said register array, wherein said RAM comprises rows and columns, comprising: (a) providing a RAM idle condition; (b) detecting attempts by said microprocessor to access a row in said RAM currently subject to accesses by said digital signal processor; (c) disabling said microprocessor from accessing said RAM either when said RAM is not in said idle condition or when said microprocessor is attempting to access a row in said RAM currently subject to accesses by said digital signal processor; and (d) enabling said microprocessor to access said RAM when said register array is in said idle condition and said microprocessor is not attempting to access a row in said RAM currently subject to accesses by said digital signal processor.

Claim 34

Dependent Claim 48 words

The method of claim 26, wherein said register array further comprises a data port, and further comprising the step of: when said microprocessor is disabled by said register array from writing data to said RAM, temporarily storing said data in said data port if said port is empty.

Claim 35

Dependent Claim 31 words

The method of claim 27, further comprising the step of: storing data stored in said data port into said RAM when said register array enables said microprocessor to access said RAM.

Claim 36

Dependent Claim 21 words

The method of claim 27, further comprising the step of: lengthening said microprocessor's input/output cycle if said data port is full.

Claim 37

Dependent Claim 32 words

The method of claim 29, further comprising the step of: storing data currently stored in said data port into said RAM when said register array enables said microprocessor to access said RAM.

Claim 38

Dependent Claim 18 words

The method of claim 30, further wherein said input/output cycle is lengthened using an input/output channel ready signal.

Claim 39

Dependent Claim 17 words

The method of claim 29, wherein said input/output cycle is lengthened using an input/output channel ready signal.

Claim 40

Independent Claim 111 words

A method of using a register array, accessible by both a microprocessor of a host computer system and a digital signal processor, to control accesses by said microprocessor and said digital signal processor of a random access memory (RAM) contained in said register array, the method comprising: (a) reading a first set of data stored in a first row of the RAM during a read cycle; (b) writing a second set of data to the first row of the RAM during a write cycle; (c) inhibiting a write to the first row of the RAM by the microprocessor during a period of time between the read cycle and the write cycle.

Claim 41

Independent Claim 111 words

A method of using a register array, accessible by both a microprocessor of a host computer system and a digital signal processor, to control accesses by said microprocessor and said digital signal processor of a random access memory (RAM) contained in said register array, the method comprising: (a) reading a first set of data stored in a first row of the RAM during a read cycle; (b) writing a second set of data to the first row of the RAM during a write cycle; (c) inhibiting a write to the first row of the RAM by the microprocessor during a period of time between the read cycle and the write cycle.

Claim 42

Dependent Claim 63 words

The method of claim 33 further comprising: during the period of time between the read cycle and the write cycle, detecting an attempt to write to a row of the RAM by the microprocessor; determining that the row attempted to be written to is the first row and inhibiting a write to the first row by said microprocessor in response to said determination.

Claim 43

Dependent Claim 85 words

The method of claim 33 further including: during the period of time between the read cycle and the write cycle, detecting an attempt to write to a row of the RAM by the microprocessor; comparing the address of the row attempted to be written by the microprocessor with the address of the first row to determine whether the row attempted to be written is the first row, and inhibiting a write by said microprocessor if said row attempted to be written is the first row.

Claim 44

Dependent Claim 44 words

The method of claim 33 wherein said register array further comprises a timing generator for timing at least the RAM input operations, and wherein inhibiting the write includes providing a gating signal to the timing generator to gate the outputs of the timing generator.

Claim 45

Dependent Claim 37 words

The method of claim 33, wherein said register array further comprises a data port, and further comprising: when the write is inhibited, temporarily storing data to be written in a data port if the port is empty.

Claim 46

Dependent Claim 21 words

The method of claim 37, further comprising: writing data stored in the data port into the RAM after the write cycle.

Claim 47

Dependent Claim 18 words

The method of claim 37, further comprising: lengthening the microprocessor's input/output cycle if the data port is full.

Claim 48

Dependent Claim 21 words

The method of claim 39, further comprising: writing data stored in the data port into the RAM after the write cycle.

Claim 49

Dependent Claim 17 words

The method of claim 39, wherein said input/output cycle is lengthened using an input/output channel ready signal.

Claim 50

Independent Claim 176 words

A method of using a register array, which is accessible by both a microprocessor of a host computer and a digital signal processor, to control accesses by said microprocessor and said digital signal processor of a random access memory (RAM) contained in said register array, wherein said RAM comprises rows, columns, and a plurality of status bits, comprising: (a) storing a value in one of said plurality of status bits, said value indicating whether data stored in a one of said rows corresponding to said one of said plurality of status bits is active; (b) reading said value from said one of said plurality of status bits, wherein said reading of said value from said one of said plurality of status bits is accomplished without causing said data to be read from said one of said rows; and (c) determining if said value indicates that said one of said rows is active; and (d) reading said data stored in said one of said rows, if said value indicates that said one of said rows is active.

Claim 51

Independent Claim 176 words

A method of using a register array, which is accessible by both a microprocessor of a host computer and a digital signal processor, to control accesses by said microprocessor and said digital signal processor of a random access memory (RAM) contained in said register array, wherein said RAM comprises rows, columns, and a plurality of status bits, comprising: (a) storing a value in one of said plurality of status bits, said value indicating whether data stored in a one of said rows corresponding to said one of said plurality of status bits is active; (b) reading said value from said one of said plurality of status bits, wherein said reading of said value from said one of said plurality of status bits is accomplished without causing said data to be read from said one of said rows; and (c) determining if said value indicates that said one of said rows is active; and (d) reading said data stored in said one of said rows, if said value indicates that said one of said rows is active.

Claim 52

Dependent Claim 99 words

The method of claim 42, further comprising: storing a value in each one of said plurality of status bits, each value indicating whether data stored in a one of said rows corresponding to said one of said plurality of status bits is active; reading each one of said plurality of status bits; and reading each one of a plurality of said rows, wherein a value stored in a one of said plurality of status bits corresponding to said each one of said plurality of said rows indicates that said each one of said plurality of said rows is active.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2003-05-02	2003-11-01	2004-05-02	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2007-05-02	2007-11-01	2008-05-02	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2011-05-02	2011-11-01	2012-05-02	$7700.00	Window Closed / Lapsed

Enhanced register array accessible by both a system microprocessor and a wavetable audio synthesizer

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