Match and match address signal prioritization in a content addressable memory encoder

Claim 3

The method as set forth in claim 1, said step of concatentating further comprising: using a first engaged bit signal to generate a blocking signal to subsequent bit signals of each of said sets.

Claim 4

A content addressable memory (CAM) circuit device comprising: a plurality of CAMs, each of said CAMs having a cell array of addressable cell means for storage of data bits therein, a MATCH signal line connected to each cell for transmitting MATCH signals on each respective said MATCH signal line, and a plurality of MATCH ADDRESS signal lines for transmitting MATCH ADDRESS signals on said respective MATCH ADDRESS signal lines; connected to each of said CAMs to receive each MATCH signal and each MATCH ADDRESS signal therefrom, a plurality of means for prioritizing said MATCH signals and said MATCH ADDRESS signals received from said CAMs on respectively connect inputs of said means for prioritizing such that only a first MATCH signal and a first MATCH ADDRESS signal from a first of said plurality of CAMS are transmitted on an output of said means for prioritizing; and means for combining bits of said first MATCH ADDRESS signal indicative of the CAM cell array in the bank providing the first MATCH signal and the first MATCH ADDRESS signal and for outputting a MATCH ADDRESS F signal designating both which said array in the bank provided the first MATCH signal and an address within said array wherein matched content data is stored in said device.

Claim 5

A content addressable memory (CAM) circuit device comprising: a plurality of CAMs, each of said CAMs having a cell array of addressable cell means for storage of data bits therein, a MATCH signal line connected to each cell for transmitting MATCH signals on each respective said MATCH signal line, and a plurality of MATCH ADDRESS signal lines for transmitting MATCH ADDRESS signals on said respective MATCH ADDRESS signal lines; connected to each of said CAMs to receive each MATCH signal and each MATCH ADDRESS signal therefrom, a plurality of means for prioritizing said MATCH signals and said MATCH ADDRESS signals received from said CAMs on respectively connect inputs of said means for prioritizing such that only a first MATCH signal and a first MATCH ADDRESS signal from a first of said plurality of CAMS are transmitted on an output of said means for prioritizing; and means for combining bits of said first MATCH ADDRESS signal indicative of the CAM cell array in the bank providing the first MATCH signal and the first MATCH ADDRESS signal and for outputting a MATCH ADDRESS F signal designating both which said array in the bank provided the first MATCH signal and an address within said array wherein matched content data is stored in said device.

Claim 6

The device as set forth in claim 3, wherein means for prioritizing said further comprises: an input buffer for receiving MATCH signals and MATCH ADDRESS signals from one of said plurality of CAMS, connected to said input buffer, a plurality of signal priority encoding circuits wherein each of said signal priority encoding circuits includes means for encoding each MATCH ADDRESS signal and means for blocking each MATCH ADDRESS signal other than said first MATCH ADDRESS signal.

Claim 7

The device as set forth in claim 4, further comprising: each of said signal priority encoding circuits having an output precharging circuit including wired-NOR circuits triggered by MATCHrow signal said CAM.

Claim 8

The device as set forth in claim 3, wherein said means for encoding further comprises: sets of wired-NOR circuits coupled to MATCH row signal lines such that only a first engaged MATCH row signal is output by each of said sets of wired-NOR circuits.

Claim 9

A content addressable memory (CAM) system with a priority encoder apparatus comprising: a plurality of CAM cores, each containing data such that redundant MATCH signals and MATCH ADDRESS signals can be output therefrom on output bit lines thereof; a plurality of priority encoders connected to receive each said MATCH signal and MATCH ADDRESS signals from one of said plurality of CAM cores, respectively, each of said priority encoders having an input signal buffer connected to each output bit line of one of said plurality of CAM cores, respectively, to receive MATCH signal bits and MATCH ADDRESS signal bits, a plurality of priority encoding circuit means, divided into N 2 sets, where N 2 =the number of MATCH ADDRESS signals inputs from each CAM core, for encoding MATCH signal bits and MATCH ADDRESS signal bits and for blocking MATCH signal bits and MATCH ADDRESS signal bits of subsequent to first active MATCH signal bits and first active MATCH ADDRESS signal bits in each set; and an address encoder for receiving MATCH signal bits, MATCH ADDRESS signal bits, blocked MATCH signal bits, and blocked MATCH ADDRESS signal bits such that only first active MATCH signal bits and first active MATCH ADDRESS signal bits are concatenated, providing only a first MATCH output signal and first MATCH ADDRESS output signal from said system.

Claim 10

A content addressable memory (CAM) system with a priority encoder apparatus comprising: a plurality of CAM cores, each containing data such that redundant MATCH signals and MATCH ADDRESS signals can be output therefrom on output bit lines thereof; a plurality of priority encoders connected to receive each said MATCH signal and MATCH ADDRESS signals from one of said plurality of CAM cores, respectively, each of said priority encoders having an input signal buffer connected to each output bit line of one of said plurality of CAM cores, respectively, to receive MATCH signal bits and MATCH ADDRESS signal bits, a plurality of priority encoding circuit means, divided into N 2 sets, where N 2 =the number of MATCH ADDRESS signals inputs from each CAM core, for encoding MATCH signal bits and MATCH ADDRESS signal bits and for blocking MATCH signal bits and MATCH ADDRESS signal bits of subsequent to first active MATCH signal bits and first active MATCH ADDRESS signal bits in each set; and an address encoder for receiving MATCH signal bits, MATCH ADDRESS signal bits, blocked MATCH signal bits, and blocked MATCH ADDRESS signal bits such that only first active MATCH signal bits and first active MATCH ADDRESS signal bits are concatenated, providing only a first MATCH output signal and first MATCH ADDRESS output signal from said system.