US6072507A
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Method and apparatus for mapping a linear address to a tiled address
Assignee: ATI Technologies ULC
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Filing: 1998-04-10
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Granted: 2000-06-06
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Expires: 2018-04-10
Abstract
Abstract A method and apparatus for mapping a linear address to a tiled address that reduces latency between retrieval of pages of data is accomplished when a video graphics processor receives a linear address from the central processing unit and determines whether the linear address is referencing a tiled surface, which is one of up to four portions of the memory. If so, the video graphics processor obtains parameters of the tiled surface. Having obtained the parameters, the video graphics processor determines a normalized linear address based on at least one of the parameters and the linear address. Having done this, the video graphics processor determines a band pointer of the tiled surface based on at least one of the parameters, the normalized linear address and a modular function. In essence, the band pointer points to a normalized initial address of a band of a tiled surface, which includes a plurality of bands. Having obtained the band pointer, the video graphics processor then determines a linear band offset based on the band pointer and at least one of the parameters. Next, a tiled band offset is determined based on the linear band offset. Finally, the tiled address is determined based on the tiled band offset, the band pointer, and at least one of the parameters.
Inventors
- 👤 Aris Balatsos
- 👤 Milivoje Aleksic
- 👤 Gordon Caruk
- 👤 Andrew E. Gruber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 02:46
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0207
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
161 words
A method for mapping a linear address to a tiled address, the method comprises the steps of: a) receiving the linear address; b) determining whether the linear address is referencing a tiled surface; c) when the linear address is referencing a tiled surface, obtaining parameters of the tiled surface; d) determining a normalized linear address based on at least one of the parameters and the linear address; e) determining a band pointer of the tiled surface based on at least one of the parameters, the normalized linear address, and a modulo function, wherein the band pointer points to a normalized initial address of a band of the tiled surface; f) determining a linear band offset based on the band pointer and at least one of the parameters; g) determining a tiled band offset based on the linear band offset; and h) determining the tiled address based on the tiled band offset, the band pointer, and at least one of the parameters.
Claim 2
Independent Claim
161 words
A method for mapping a linear address to a tiled address, the method comprises the steps of: a) receiving the linear address; b) determining whether the linear address is referencing a tiled surface; c) when the linear address is referencing a tiled surface, obtaining parameters of the tiled surface; d) determining a normalized linear address based on at least one of the parameters and the linear address; e) determining a band pointer of the tiled surface based on at least one of the parameters, the normalized linear address, and a modulo function, wherein the band pointer points to a normalized initial address of a band of the tiled surface; f) determining a linear band offset based on the band pointer and at least one of the parameters; g) determining a tiled band offset based on the linear band offset; and h) determining the tiled address based on the tiled band offset, the band pointer, and at least one of the parameters.
Claim 3
Dependent Claim
28 words
The method of claim 1, wherein step c) further comprises obtaining an initial address of the tiled surface and a pitch of the tiled surface as the parameters.
Claim 4
Dependent Claim
35 words
The method of claim 2 further comprises obtaining a pixel size, an N value, and a k value as the parameters, wherein the N and k values are based on the pitch of k*2 N.
Claim 5
Dependent Claim
71 words
The method of claim 3, wherein step (e) further comprises right shifting the linear address by the N value to produce a shifted address value, performing the modulo function upon the shifted address value, based on the k value, to obtain a modulo value, subtracting the modulo value from the shifted address value to produce a resultant, and left shifting the resultant by the N value to produce the band pointer.
Claim 6
Dependent Claim
54 words
The method of claim 3, wherein step (g) further comprises, when the k value equals one, determining an x value and a y value for the band, where the x value is obtained from LSBs of the linear band offset and the y value is obtained from the MSBs of the linear band offset.
Claim 7
Dependent Claim
41 words
The method of claim 5 further comprises combining the x value and the y value to obtain the tiled band offset, wherein the x value and y value are combined based on (x[MSB:x i ], y[y i :0], x[x i :0]).
Claim 8
Dependent Claim
62 words
The method of claim 3, wherein step (g) further comprises, when the k value is not equal to one, determining an x value and a y value based on a DIV function of the linear band offset and the pitch that produces a DIV value and a MOD function of the linear band offset and the pitch that produces a MOD value.
Claim 9
Dependent Claim
29 words
The method of claim 7 further comprises accessing a look-up table based on the DIV value and the MOD value to obtain the x value and the y value.
Claim 10
Dependent Claim
24 words
The method of claim 1, wherein step (f) further comprises subtracting the band pointer from the linear address to obtain the linear band offset.
Claim 11
Independent Claim
124 words
A method for mapping a linear address to a tiled address, the method comprises the steps of: a) determining a surface offset value of a tiled surface based on a linear address; b) determining a normalized linear address based on the surface offset value, a pitch, and the linear address; c) determining a band pointer of the tiled surface based on the surface offset value, the normalized linear address, and a modulo function, wherein the band pointer points to a normalized initial address of a band of the tiled surface; d) determining a tiled band offset based on the band pointer and the pitch, and e) determining the tiled address based on the tiled band offset, the band pointer, and the surface offset value.
Claim 12
Independent Claim
124 words
A method for mapping a linear address to a tiled address, the method comprises the steps of: a) determining a surface offset value of a tiled surface based on a linear address; b) determining a normalized linear address based on the surface offset value, a pitch, and the linear address; c) determining a band pointer of the tiled surface based on the surface offset value, the normalized linear address, and a modulo function, wherein the band pointer points to a normalized initial address of a band of the tiled surface; d) determining a tiled band offset based on the band pointer and the pitch, and e) determining the tiled address based on the tiled band offset, the band pointer, and the surface offset value.
Claim 13
Dependent Claim
35 words
The method of claim 10, wherein step (d) further comprises determining a linear band offset based on the band pointer and the pitch and determining the tiled band offset based on the linear band offset.
Claim 14
Dependent Claim
33 words
The method of claim 10, wherein the pitch comprises an N value and a k value, wherein the N and k values are related to the pitch based on the equation k*2 N.
Claim 15
Dependent Claim
71 words
The method of claim 12, wherein step (c) further comprises right shifting the linear address by the N value to produce a shifted address value, performing the modulo function upon the shifted address value, based on the k value, to obtain a modulo value, subtracting the modulo value from the shifted address value to produce a resultant, and left shifting the resultant by the N value to produce the band pointer.
Claim 16
Dependent Claim
54 words
The method of claim 12, wherein step (d) further comprises, when the k value equals one, determining an x value and a y value for the band, where the x value is obtained from LSBs of the linear band offset and the y value is obtained from the MSBs of the linear band offset.
Claim 17
Dependent Claim
41 words
The method of claim 14 further comprises combining the x value and the y value to obtain the tiled band offset, wherein the x value and y value are combined based on (x[MSB:x i ], y[y i :0], x[x i :0]).
Claim 18
Dependent Claim
62 words
The method of claim 12, wherein step (d) further comprises, when the k value is not equal to one, determining an x value and a y value based on a DIV function of the linear band offset and the pitch that produces a DIV value and a MOD function of the linear band offset and the pitch that produces a MOD value.
Claim 19
Dependent Claim
29 words
The method of claim 16 further comprises accessing a look-up table based on the DIV value and the MOD value to obtain the x value and the y value.
Claim 20
Dependent Claim
224 words
A mapping circuit that maps a linear address to a tiled address of a memory, the mapping circuit comprises: surface detection circuit operably coupled to receive the linear address and determines whether the linear address identifies a tiled surface in the memory; parameter circuit operably coupled to the surface detection circuit, wherein the parameter circuit provides parameters of the tiled surface when the linear address identifies the tiled surface; address normalization circuit operably coupled to the receive the linear address and the parameters, wherein the address normalization circuit generates a normalized linear address based on the linear address and at least one of the parameters; tiled band offset circuit operably coupled to receive the normalized linear address and at least one of the parameters and generates, therefrom, a tiled band offset, wherein the tiled band offset circuit includes: band pointer circuit operably coupled to receive the normalized linear address and to produce therefrom, based on a modulo function, a band pointer; linear band offset circuit operably coupled to receive the band pointer and at least one of the parameters and to produce therefrom a linear band offset; tiling circuit operably coupled to receive the linear band offset and to produce therefrom the tiled band offset; and tiled address circuit operably coupled to receive the tiled band offset and to produce therefrom the tiled address.
Claim 21
Dependent Claim
224 words
A mapping circuit that maps a linear address to a tiled address of a memory, the mapping circuit comprises: surface detection circuit operably coupled to receive the linear address and determines whether the linear address identifies a tiled surface in the memory; parameter circuit operably coupled to the surface detection circuit, wherein the parameter circuit provides parameters of the tiled surface when the linear address identifies the tiled surface; address normalization circuit operably coupled to the receive the linear address and the parameters, wherein the address normalization circuit generates a normalized linear address based on the linear address and at least one of the parameters; tiled band offset circuit operably coupled to receive the normalized linear address and at least one of the parameters and generates, therefrom, a tiled band offset, wherein the tiled band offset circuit includes: band pointer circuit operably coupled to receive the normalized linear address and to produce therefrom, based on a modulo function, a band pointer; linear band offset circuit operably coupled to receive the band pointer and at least one of the parameters and to produce therefrom a linear band offset; tiling circuit operably coupled to receive the linear band offset and to produce therefrom the tiled band offset; and tiled address circuit operably coupled to receive the tiled band offset and to produce therefrom the tiled address.
Claim 22
Dependent Claim
47 words
The mapping circuit of claim 18, wherein the parameters comprise an initial address of the tiled surface, a pitch of the tiled surface, a pixel size, an N value, and a k value, wherein the N and k values are based on the pitch of k*2 N.
Claim 23
Dependent Claim
110 words
The mapping circuit of claim 19, wherein the band pointer circuit comprises: a right shift register operably coupled to shift the linear band offset by the N value to produce a shifted address value; a modulo circuit operably coupled to receive the k value and the shifted address value, wherein the modulo circuit performs a modulo function upon the shifted address value based on the k value to obtain a modulo value, subtraction circuit operably coupled to subtract the modulo value from the shifted address value to produce a resultant; and a left shift register operably coupled to shift the resultant by the N value to produce the band pointer.
Claim 24
Dependent Claim
210 words
The mapping circuit of claim 19, wherein the tiling circuit further comprises: a first circuit operably coupled to receive the linear band offset when the k value equals one, wherein the first circuit determining an x value and a y value for the band, where the x value is obtained from LSBs of the linear band offset and the y value is obtained from the MSBs of the linear band offset; a second circuit operably coupled to receive the linear band offset when the k value is not equal to one, the second circuit determines a DIV value based on a DIV function of the linear band offset and the pitch and a MOD value based on a MOD function of the linear band offset and the pitch; and a look-up table operably coupled to the second circuit, wherein the look-up table is accessed based on the DIV value and the MOD value to obtain the x value and the y value; and a combining circuit operably coupled to the first circuit, wherein the combining circuit combining the x value and the y value to obtain the tiled band offset, wherein the x value and y value are combined based on (x[MSB:x i ], y[y i :0], x[x i :0]).
Claim 25
Dependent Claim
155 words
A mapping circuit that maps a linear address to a tiled address of a memory, the mapping circuit comprises: a processing unit; and memory operably coupled to the processing unit, wherein the memory stores programming instructions that, when read by the processing unit, cause the processing unit to obtain parameters of a tiled surface based on a linear address; determine a normalized linear address based on at least one of the parameters and the linear address; determine a band pointer of the tiled surface based on at least one of the parameters, the normalized linear address, and a modulo function, wherein the band pointer points to a normalized initial address of a band of the tiled surface; determine a tiled band offset based on the band pointer and at least one of the parameters; and determine the tiled address based on the tiled band offset, the band pointer, and at least one of the parameters.
Claim 26
Dependent Claim
155 words
A mapping circuit that maps a linear address to a tiled address of a memory, the mapping circuit comprises: a processing unit; and memory operably coupled to the processing unit, wherein the memory stores programming instructions that, when read by the processing unit, cause the processing unit to obtain parameters of a tiled surface based on a linear address; determine a normalized linear address based on at least one of the parameters and the linear address; determine a band pointer of the tiled surface based on at least one of the parameters, the normalized linear address, and a modulo function, wherein the band pointer points to a normalized initial address of a band of the tiled surface; determine a tiled band offset based on the band pointer and at least one of the parameters; and determine the tiled address based on the tiled band offset, the band pointer, and at least one of the parameters.
Claim 27
Dependent Claim
47 words
The mapping circuit of claim 22, wherein the parameters comprise an initial address of the tiled surface, a pitch of the tiled surface, a pixel size, an N value, and a k value, wherein the N and k values are based on the pitch of k*2 N.
Claim 28
Dependent Claim
44 words
The mapping circuit of claim 23, wherein the memory further comprises programming instructions that cause the processing unit to determine a linear band offset based on the band pointer and the pitch and determining the tiled band offset based on the linear band offset.
Claim 29
Dependent Claim
80 words
The mapping circuit of claim 23, wherein the memory further comprises programming instructions that cause the processing unit to right shift the linear address by the N value to produce a shifted address value, perform the modulo function upon the shifted address value, based on the k value, to obtain a modulo value, subtract the modulo value from the shifted address value to produce a resultant, and left shift the resultant by the N value to produce the band pointer.
Claim 30
Dependent Claim
63 words
The mapping circuit of claim 23, wherein the memory further comprises programming instructions that cause the processing unit to determine an x value and a y value for the band when the k value equals one, where the x value is obtained from LSBs of the linear band offset and the y value is obtained from the MSBs of the linear band offset.
Claim 31
Dependent Claim
53 words
The mapping circuit of claim 26, wherein the memory further comprises programming instructions that cause the processing unit to combine the x value and the y value to obtain the tiled band offset, wherein the x value and y value are combined based on (x[MSB:x i ], y[y i :0], x[x i :0]).
Claim 32
Dependent Claim
71 words
The mapping circuit of claim 23, wherein the memory further comprises programming instructions that cause the processing unit to determine an x value and a y value based on a DIV function of the linear band offset and the pitch that produces a DIV value and a MOD function of the linear band offset and the pitch that produces a MOD value when the k value is not equal to one.
Claim 33
Dependent Claim
41 words
The mapping circuit of claim 23, wherein the memory further comprises programming instructions that cause the processing unit to access a look-up table based on the DIV value and the MOD value to obtain the x value and the y value.
Claim 34
Dependent Claim
255 words
A video graphics circuit comprising: a video processor operably coupled to provide pixel data to a display; memory operably coupled to store the pixel data prior to being displayed on the display; and a mapping circuit operably coupled to the video processor and the memory, wherein the mapping circuit includes: surface detection circuit operably coupled to receive the linear address and determines whether the linear address identifies a tiled surface in the memory; parameter circuit operably coupled to the surface detection circuit wherein the parameter circuit provides parameters of the tiled surface when the linear address identifies the tiled surface; address normalization circuit operably coupled to the receive the linear address and the parameters, wherein the address normalization circuit generates a normalized linear address based on the linear address and at least one of the parameters; tiled band offset circuit operably coupled to receive the normalized linear address and at least one of the parameters and generates, therefrom a tiled band offset, wherein the tiled band offset circuit includes: band pointer circuit operably coupled to receive the normalized linear address and to produce therefrom, based on a modulo function, a band pointer; linear band offset circuit operably coupled to receive the band pointer and at least one of the parameters and to produce therefrom a linear band offset; tiling circuit operably coupled to receive the linear band offset and to produce therefrom the tiled band offset; and tiled address circuit operably coupled to receive the tiled band offset and to produce therefrom the tiled address.
Claim 35
Dependent Claim
255 words
A video graphics circuit comprising: a video processor operably coupled to provide pixel data to a display; memory operably coupled to store the pixel data prior to being displayed on the display; and a mapping circuit operably coupled to the video processor and the memory, wherein the mapping circuit includes: surface detection circuit operably coupled to receive the linear address and determines whether the linear address identifies a tiled surface in the memory; parameter circuit operably coupled to the surface detection circuit wherein the parameter circuit provides parameters of the tiled surface when the linear address identifies the tiled surface; address normalization circuit operably coupled to the receive the linear address and the parameters, wherein the address normalization circuit generates a normalized linear address based on the linear address and at least one of the parameters; tiled band offset circuit operably coupled to receive the normalized linear address and at least one of the parameters and generates, therefrom a tiled band offset, wherein the tiled band offset circuit includes: band pointer circuit operably coupled to receive the normalized linear address and to produce therefrom, based on a modulo function, a band pointer; linear band offset circuit operably coupled to receive the band pointer and at least one of the parameters and to produce therefrom a linear band offset; tiling circuit operably coupled to receive the linear band offset and to produce therefrom the tiled band offset; and tiled address circuit operably coupled to receive the tiled band offset and to produce therefrom the tiled address.
Claim 36
Dependent Claim
48 words
The video graphics circuit of claim 30, wherein the parameters comprise an initial address of the tiled surface, a pitch of the tiled surface, a pixel size, an N value, and a k value, wherein the N and k values are based on the pitch of k*2 N.
Claim 37
Dependent Claim
111 words
The video graphics circuit of claim 31, wherein the band pointer circuit comprises: a right shift register operably coupled to shift the linear band offset by the N value to produce a shifted address value; a modulo circuit operably coupled to receive the k value and the shifted address value, wherein the modulo circuit performs a modulo function upon the shifted address value based on the k value to obtain a modulo value, subtraction circuit operably coupled to subtract the modulo value from the shifted address value to produce a resultant; and a left shift register operably coupled to shift the resultant by the N value to produce the band pointer.
Claim 38
Dependent Claim
211 words
The video graphics circuit of claim 31, wherein the tiling circuit further comprises: a first circuit operably coupled to receive the linear band offset when the k value equals one, wherein the first circuit determining an x value and a y value for the band, where the x value is obtained from LSBs of the linear band offset and the y value is obtained from the MSBs of the linear band offset; a second circuit operably coupled to receive the linear band offset when the k value is not equal to one, the second circuit determines a DIV value based on a DIV function of the linear band offset and the pitch and a MOD value based on a MOD function of the linear band offset and the pitch; and a look-up table operably coupled to the second circuit, wherein the look-up table is accessed based on the DIV value and the MOD value to obtain the x value and the y value; and a combining circuit operably coupled to the first circuit, wherein the combining circuit combining the x value and the y value to obtain the tiled band offset, wherein the x value and y value are combined based on (x[MSB:x i ], y[y i :0], x[x i :0]).
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-06 | 2003-12-06 | 2004-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-06 | 2007-12-06 | 2008-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-06 | 2011-12-06 | 2012-06-06 | $7700.00 | Window Closed / Lapsed |