US6077308A
Expired / Lapsed
US
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Creating layout for integrated circuit structures
Assignee: Micron Technology Inc
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Filing: 1997-08-21
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Granted: 2000-06-20
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Expires: 2017-08-21
Abstract
Abstract A method and system for constructing polygon layout. From a schematic, there is a data file describing a series-parallel transistor structure having a plurality of gate regions and a plurality of source/drain regions. A representation list is created (either by a computer user or by a computer analyzing a netlist). This representation list includes a plurality of region data for the plurality of gate regions and the plurality of source/drain regions. Polygon layout is built for the series-parallel transistor structure from this representation list.
Inventors
- 👤 Craig A. Carter
- 👤 John D. Mosby
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 17:52
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
247 words
A computer readable medium having computer readable instructions for: creating a schematic for representing a circuit design, wherein the schematic comprises a plurality of instances and a plurality of nets; translating the schematic into a netlist file, wherein the netlist file is a text file describing each of the plurality of instances; synthesizing the netlist file, wherein synthesizing comprises analyzing the connectivity of the plurality of instances by the plurality of nets, and choosing a first plurality of objects to place, wherein the first plurality of objects comprise a plurality of gate regions and a plurality of source/drain regions; determining relative placement locations for the first plurality of objects, wherein relative placement means the placement in relation to the rest of the first plurality of objects; determining a second plurality of objects from the first plurality of objects, wherein the second plurality of objects can be merged into a series-parallel transistor structure; building a polygon layout for the series-parallel transistor structure representing the second plurality of objects, wherein building comprises creating a representation list for the plurality of gate regions and the plurality of source/drain regions from the second plurality of objects, wherein the representation list includes a plurality of region data individually describing the plurality of source/drain regions and the plurality of gate regions, and constructing a polygon for the series-parallel transistor structure from the representation list based on the plurality of region data; and storing the polygon layout to a layout database in a memory.
Claim 2
Dependent Claim
247 words
A computer readable medium having computer readable instructions for: creating a schematic for representing a circuit design, wherein the schematic comprises a plurality of instances and a plurality of nets; translating the schematic into a netlist file, wherein the netlist file is a text file describing each of the plurality of instances; synthesizing the netlist file, wherein synthesizing comprises analyzing the connectivity of the plurality of instances by the plurality of nets, and choosing a first plurality of objects to place, wherein the first plurality of objects comprise a plurality of gate regions and a plurality of source/drain regions; determining relative placement locations for the first plurality of objects, wherein relative placement means the placement in relation to the rest of the first plurality of objects; determining a second plurality of objects from the first plurality of objects, wherein the second plurality of objects can be merged into a series-parallel transistor structure; building a polygon layout for the series-parallel transistor structure representing the second plurality of objects, wherein building comprises creating a representation list for the plurality of gate regions and the plurality of source/drain regions from the second plurality of objects, wherein the representation list includes a plurality of region data individually describing the plurality of source/drain regions and the plurality of gate regions, and constructing a polygon for the series-parallel transistor structure from the representation list based on the plurality of region data; and storing the polygon layout to a layout database in a memory.
Claim 3
Dependent Claim
45 words
The computer readable medium, as recited in claim 1, having further instructions that, when executed, cause the computer to create the representation list at least in part by creating the plurality of region data comprising region connectivity data, physical characteristics data, and electrical characteristics data.
Claim 4
Dependent Claim
30 words
The computer readable medium, as recited in claim 1, having further instructions that, when executed, cause the computer to build the polygon layout according to a plurality of design rules.
Claim 5
Dependent Claim
28 words
The computer readable medium, as recited in claim 1, having further instructions that, when executed, cause the computer to create the representation list from analysis of a netlist.
Claim 6
Dependent Claim
34 words
The computer readable medium, as recited in claim 1, having further instructions that, when executed, cause the computer to create the representation list at least in part by accepting data from a computer user.
Claim 7
Independent Claim
248 words
A method for designing an integrated circuit, the method comprising: creating a schematic for representing a circuit design, wherein the schematic comprises a plurality of instances and a plurality of nets; translating the schematic into a netlist file, wherein the netlist file is a text file describing each of the plurality of instances; synthesizing the netlist file, wherein synthesizing comprises analyzing the connectivity of the plurality of instances by the plurality of nets, and choosing a first plurality of objects to place, wherein the first plurality of objects comprise a plurality of gate regions and a plurality of source/drain regions; determining relative placement locations for the first plurality of objects, wherein relative placement means the placement in relation to the rest of the first plurality of objects; determining a second plurality of objects from the first plurality of objects, wherein the second plurality of objects can be merged into a series-parallel transistor structure; building a polygon layout for the series-parallel transistor structure representing the second plurality of objects, wherein building comprises creating a representation list for the plurality of gate regions and the plurality of source/drain regions from the second plurality of objects, wherein the representation list includes a plurality of region data individually describing the plurality of source/drain regions and the plurality of gate regions, and constructing a polygon for the series-parallel transistor structure from the representation list based on the plurality of region data; and storing the polygon layout to a layout database in a memory.
Claim 8
Independent Claim
248 words
A method for designing an integrated circuit, the method comprising: creating a schematic for representing a circuit design, wherein the schematic comprises a plurality of instances and a plurality of nets; translating the schematic into a netlist file, wherein the netlist file is a text file describing each of the plurality of instances; synthesizing the netlist file, wherein synthesizing comprises analyzing the connectivity of the plurality of instances by the plurality of nets, and choosing a first plurality of objects to place, wherein the first plurality of objects comprise a plurality of gate regions and a plurality of source/drain regions; determining relative placement locations for the first plurality of objects, wherein relative placement means the placement in relation to the rest of the first plurality of objects; determining a second plurality of objects from the first plurality of objects, wherein the second plurality of objects can be merged into a series-parallel transistor structure; building a polygon layout for the series-parallel transistor structure representing the second plurality of objects, wherein building comprises creating a representation list for the plurality of gate regions and the plurality of source/drain regions from the second plurality of objects, wherein the representation list includes a plurality of region data individually describing the plurality of source/drain regions and the plurality of gate regions, and constructing a polygon for the series-parallel transistor structure from the representation list based on the plurality of region data; and storing the polygon layout to a layout database in a memory.
Claim 9
Dependent Claim
31 words
The method, as recited in claim 6, wherein creating a representation list further includes creating the plurality of region data comprising region connectivity data, physical characteristics data, and electrical characteristics data.
Claim 10
Dependent Claim
15 words
The method, as recited in claim 6, wherein building observes a plurality of design rules.
Claim 11
Dependent Claim
23 words
The method, as recited in claim 6, wherein creating a representation list is performed by a computer system from analysis of a netlist.
Claim 12
Dependent Claim
24 words
The method, as recited in claim 6, wherein creating a representation list is performed by a computer system accepting data from a computer user.
Claim 13
Dependent Claim
243 words
A computer arrangement configured to: create a schematic for representing a circuit design, wherein the schematic comprises a plurality of instances and a plurality of nets; translate the schematic into a netlist file, wherein the netlist file is a text file describing each of the plurality of instances; synthesize the netlist file, wherein synthesizing comprises analyzing the connectivity of the plurality of instances by the plurality of nets, and choosing a first plurality of objects to place, wherein the first plurality of objects comprise a plurality of gate regions and a plurality of source/drain regions; determine relative placement locations for the first plurality of objects, wherein relative placement means the placement in relation to the rest of the first plurality of objects; determine a second plurality of objects from the first plurality of objects, wherein the second plurality of objects can be merged into a series-parallel transistor structure; build a polygon layout for the series-parallel transistor structure representing the second plurality of objects, wherein building comprises creating a representation list for the plurality of gate regions and the plurality of source/drain regions from the second plurality of objects, wherein the representation list includes a plurality of region data individually describing the plurality of source/drain regions and the plurality of gate regions, and constructing a polygon for the series-parallel transistor structure from the representation list based on the plurality of region data; and store the polygon layout to a layout database in a memory.
Claim 14
Dependent Claim
243 words
A computer arrangement configured to: create a schematic for representing a circuit design, wherein the schematic comprises a plurality of instances and a plurality of nets; translate the schematic into a netlist file, wherein the netlist file is a text file describing each of the plurality of instances; synthesize the netlist file, wherein synthesizing comprises analyzing the connectivity of the plurality of instances by the plurality of nets, and choosing a first plurality of objects to place, wherein the first plurality of objects comprise a plurality of gate regions and a plurality of source/drain regions; determine relative placement locations for the first plurality of objects, wherein relative placement means the placement in relation to the rest of the first plurality of objects; determine a second plurality of objects from the first plurality of objects, wherein the second plurality of objects can be merged into a series-parallel transistor structure; build a polygon layout for the series-parallel transistor structure representing the second plurality of objects, wherein building comprises creating a representation list for the plurality of gate regions and the plurality of source/drain regions from the second plurality of objects, wherein the representation list includes a plurality of region data individually describing the plurality of source/drain regions and the plurality of gate regions, and constructing a polygon for the series-parallel transistor structure from the representation list based on the plurality of region data; and store the polygon layout to a layout database in a memory.
Claim 15
Dependent Claim
37 words
The computer arrangement, as recited in claim 11, further configured to create the representation list at least in part by creating the plurality of region data comprising region connectivity data, physical characteristics data, and electrical characteristics data.
Claim 16
Dependent Claim
22 words
The computer arrangement, as recited in claim 11, further configured to build the polygon layout according to a plurality of design rules.
Claim 17
Dependent Claim
20 words
The computer arrangement, as recited in claim 11, further configured to create the representation list from analysis of a netlist.
Claim 18
Dependent Claim
26 words
The computer arrangement, as recited in claim 11, further configured to create the representation list at least in part by accepting data from a computer user.
Claim 19
Independent Claim
251 words
A device generator comprising: a computer readable medium having computer readable instructions for creating a schematic for representing a circuit design, wherein the schematic comprises a plurality of instances and a plurality of nets; translating the schematic into a netlist file, wherein the netlist file is a text file describing each of the plurality of instances; synthesizing the netlist file, wherein synthesizing comprises analyzing the connectivity of the plurality of instances by the plurality of nets, and choosing a first plurality of objects to place, wherein the first plurality of objects comprise a plurality of gate regions and a plurality of source/drain regions; determining relative placement locations for the first plurality of objects, wherein relative placement means the placement in relation to the rest of the first plurality of objects; determining a second plurality of objects from the first plurality of objects, wherein the second plurality of objects can be merged into a series-parallel transistor structure; building a polygon layout for the series-parallel transistor structure representing the second plurality of objects, wherein building comprises creating a representation list for the plurality of gate regions and the plurality of source/drain regions from the second plurality of objects, wherein the representation list includes a plurality of region data individually describing the plurality of source/drain regions and the plurality of gate regions, and constructing a polygon for the series-parallel transistor structure from the representation list based on the plurality of region data; and storing the polygon layout to a layout database in a memory.
Claim 20
Independent Claim
251 words
A device generator comprising: a computer readable medium having computer readable instructions for creating a schematic for representing a circuit design, wherein the schematic comprises a plurality of instances and a plurality of nets; translating the schematic into a netlist file, wherein the netlist file is a text file describing each of the plurality of instances; synthesizing the netlist file, wherein synthesizing comprises analyzing the connectivity of the plurality of instances by the plurality of nets, and choosing a first plurality of objects to place, wherein the first plurality of objects comprise a plurality of gate regions and a plurality of source/drain regions; determining relative placement locations for the first plurality of objects, wherein relative placement means the placement in relation to the rest of the first plurality of objects; determining a second plurality of objects from the first plurality of objects, wherein the second plurality of objects can be merged into a series-parallel transistor structure; building a polygon layout for the series-parallel transistor structure representing the second plurality of objects, wherein building comprises creating a representation list for the plurality of gate regions and the plurality of source/drain regions from the second plurality of objects, wherein the representation list includes a plurality of region data individually describing the plurality of source/drain regions and the plurality of gate regions, and constructing a polygon for the series-parallel transistor structure from the representation list based on the plurality of region data; and storing the polygon layout to a layout database in a memory.
Claim 21
Dependent Claim
49 words
The device generator, as recited in claim 16, wherein the computer readable medium has further instructions that, when executed, cause the computer to create the representation list at least in part by creating the plurality of region data comprising region connectivity data, physical characteristics data, and electrical characteristics data.
Claim 22
Dependent Claim
34 words
The device generator, as recited in claim 16, wherein the computer readable medium has further instructions that, when executed, cause the computer to build the polygon layout according to a plurality of design rules.
Claim 23
Dependent Claim
32 words
The device generator, as recited in claim 16, wherein the computer readable medium has further instructions that, when executed, cause the computer to create the representation list from analysis of a netlist.
Claim 24
Dependent Claim
38 words
The device generator, as recited in claim 16, wherein the computer readable medium has further instructions that, when executed, cause the computer to create the representation list at least in part by accepting data from a computer user.
Claim 25
Independent Claim
247 words
A device generator comprising: a computer arrangement configured to create a schematic for representing a circuit design, wherein the schematic comprises a plurality of instances and a plurality of nets; translate the schematic into a netlist file, wherein the netlist file is a text file describing each of the plurality of instances; synthesize the netlist file, wherein synthesizing comprises analyzing the connectivity of the plurality of instances by the plurality of nets, and choosing a first plurality of objects to place, wherein the first plurality of objects comprise a plurality of gate regions and a plurality of source/drain regions; determine relative placement locations for the first plurality of objects, wherein relative placement means the placement in relation to the rest of the first plurality of objects; determine a second plurality of objects from the first plurality of objects, wherein the second plurality of objects can be merged into a series-parallel transistor structure; build a polygon layout for the series-parallel transistor structure representing the second plurality of objects, wherein building comprises creating a representation list for the plurality of gate regions and the plurality of source/drain regions from the second plurality of objects, wherein the representation list includes a plurality of region data individually describing the plurality of source/drain regions and the plurality of gate regions, and constructing a polygon for the series-parallel transistor structure from the representation list based on the plurality of region data; and store the polygon layout to a layout database in a memory.
Claim 26
Independent Claim
247 words
A device generator comprising: a computer arrangement configured to create a schematic for representing a circuit design, wherein the schematic comprises a plurality of instances and a plurality of nets; translate the schematic into a netlist file, wherein the netlist file is a text file describing each of the plurality of instances; synthesize the netlist file, wherein synthesizing comprises analyzing the connectivity of the plurality of instances by the plurality of nets, and choosing a first plurality of objects to place, wherein the first plurality of objects comprise a plurality of gate regions and a plurality of source/drain regions; determine relative placement locations for the first plurality of objects, wherein relative placement means the placement in relation to the rest of the first plurality of objects; determine a second plurality of objects from the first plurality of objects, wherein the second plurality of objects can be merged into a series-parallel transistor structure; build a polygon layout for the series-parallel transistor structure representing the second plurality of objects, wherein building comprises creating a representation list for the plurality of gate regions and the plurality of source/drain regions from the second plurality of objects, wherein the representation list includes a plurality of region data individually describing the plurality of source/drain regions and the plurality of gate regions, and constructing a polygon for the series-parallel transistor structure from the representation list based on the plurality of region data; and store the polygon layout to a layout database in a memory.
Claim 27
Dependent Claim
42 words
The device generator, as recited in claim 21, wherein the computer arrangement is further configured to create the representation list at least in part by creating the plurality of region data comprising region connectivity data, physical characteristics data, and electrical characteristics data.
Claim 28
Dependent Claim
27 words
The device generator, as recited in claim 21, wherein the computer arrangement is further configured to build the polygon layout according to a plurality of design rules.
Claim 29
Dependent Claim
25 words
The device generator, as recited in claim 21, wherein the computer arrangement is further configured to create the representation list from analysis of a netlist.
Claim 30
Dependent Claim
31 words
The device generator, as recited in claim 21, wherein the computer arrangement is further configured to create the representation list at least in part by accepting data from a computer user.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-20 | 2003-12-20 | 2004-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-20 | 2007-12-20 | 2008-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-20 | 2011-12-20 | 2012-06-20 | $7700.00 | Window Closed / Lapsed |