US6137718A
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Method for operating a non-volatile memory cell arrangement
Assignee: Infineon Technologies AG
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Filing: 1997-07-08
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Granted: 2000-10-24
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Expires: 2017-07-08
Abstract
Abstract PCT No. PCT/DE97/01432 Sec. 371 Date Jan. 28, 1999 Sec. 102(e) Date Jan. 28, 1999 PCT Filed Jul. 8, 1997 PCT Pub. No. WO98/06101 PCT Pub. Date Feb. 12, 1998In order to increase the storage density, in a memory cell arrangement having MOS transistors as memory cells which has as gate dielectric, a dielectric triple layer having a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer, the silicon oxide layers each having a thickness of at least 3 nm, the information is stored using multi-value logic with up to 26 values. In this case, use is made of the fact that these memory cells have a time period greater than 1000 years for data retention and their threshold voltage has a very small drift.
Inventors
- 👤 Hans Reisinger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 02:15
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; H; H10; H10D; H10D30/00; H10D30/60; H10D30/69; H10D30/691; G11C11/5621; G11C11/5628; G11C11/5671
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
150 words
A method for operating a memory cell arrangement, comprising the steps of: providing memory cells having MOS transistors; providing said MOS transistors with a gate dielectric including a dielectric triple layer having a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer; providing the first silicon oxide layer and the second silicon oxide layer each with a thickness of at least 3 nm; using multi-value logic with more than two logic values to store information; applying a respective quantity of charge assigned to the respective logic value to the gate dielectric by Fowler-Nordheim tunneling for writing a respective logic value of the more than two logic values to one of the memory cells; and storing the respective quantity of charge in the gate dielectric, said quantity of charge effects a threshold voltage level of the MOS transistor which is assigned to the respective logic value.
Claim 2
Independent Claim
150 words
A method for operating a memory cell arrangement, comprising the steps of: providing memory cells having MOS transistors; providing said MOS transistors with a gate dielectric including a dielectric triple layer having a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer; providing the first silicon oxide layer and the second silicon oxide layer each with a thickness of at least 3 nm; using multi-value logic with more than two logic values to store information; applying a respective quantity of charge assigned to the respective logic value to the gate dielectric by Fowler-Nordheim tunneling for writing a respective logic value of the more than two logic values to one of the memory cells; and storing the respective quantity of charge in the gate dielectric, said quantity of charge effects a threshold voltage level of the MOS transistor which is assigned to the respective logic value.
Claim 3
Dependent Claim
26 words
The method as claimed in claim 1, further comprising the step of: increasing an amount separating neighboring threshold voltage levels as the threshold voltage level increases.
Claim 4
Dependent Claim
91 words
The method as claimed in claim 1, wherein a difference between thicknesses of the first silicon oxide layer and the second silicon oxide layer lies in a range between 0.5 nm and 1 nm, wherein a smaller of the thicknesses of the first silicon oxide layer and of the second silicon oxide layer lies in a range between 3 nm and 6 nm, wherein the silicon nitride layer has a thickness of at least 5 nm, and wherein each of the MOS transistors has a gate electrode made of n-doped silicon.
Claim 5
Dependent Claim
25 words
The method as claimed in claim 3, further comprising the step of: using multi-value logic with 2n values, where n is between 2 and 6.
Claim 6
Dependent Claim
92 words
The method as claimed in claim 1, wherein a difference between thicknesses of the first silicon oxide layer and the second silicon oxide layer lies in a range between 0.5 nm and 1 nm, wherein a smaller of the thicknesses of the first silicon oxide layer and of the second silicon oxide layer lies in a range between 3.2 and 4 nm, wherein the silicon nitride layer has a thickness of at least 5 nm, and wherein each of the MOS transistors has a gate electrode made of p + -doped silicon.
Claim 7
Dependent Claim
28 words
The method as claimed in claim 5, wherein p + -doped silicon in the gate electrode has a dopant concentration of at least 1×10 20 cm -3 .
Claim 8
Dependent Claim
25 words
The method as claimed in claim 5, further comprising the step of: using multi-value logic with 2n values, where n is between 2 and 3.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-24 | 2004-04-24 | 2004-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-24 | 2008-04-24 | 2008-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-24 | 2012-04-24 | 2012-10-24 | $7700.00 | Window Closed / Lapsed |