Semiconductor memory device and fabricating method

Claim 2

A semiconductor memory device comprising: an SOI substrate formed on a first silicon layer, said SOI substrate including an insulating layer formed on said first silicon layer and a second silicon layer formed on said insulating layer; a shallow trench isolation structure formed in said SOI substrate, wherein said shallow trench isolation structure extends through said second silicon layer and into said insulating layer of said SOI substrate to thereby define an isolated active area of said second silicon layer; a MOS transistor formed on said active area; a trench formed in the vicinity of said MOS transistor, said trench extending through said SOI substrate and into said first silicon layer; and a conductive film buried in said insulating layer of said SOI substrate, said conductive film being in contact with said trench, said conductive film extending toward said MOS transistor from said trench beyond a side portion of said trench and being in contact with a bottom surface of one of source/drain electrodes of said MOS transistor.

Claim 3

A semiconductor memory device comprising: a substrate formed on first semiconductor layer, said substrate comprising an insulating layer formed on said first semiconductor layer and a second semiconductor layer formed on said insulating layer; a shallow trench isolation structure formed in said substrate, wherein said shallow trench isolation structure extends through said second semiconductor layer and into said insulating layer of said substrate to thereby define an isolated active area of said second semiconductor layer; a MOS transistor formed on said active area; a trench located in the vicinity of said MOS transistor and reaching said first semiconductor layer through said second semiconductor layer and said insulating layer; a first conductive material filling in said trench; and a second conductive material formed in an etched portion of said insulating layer, which portion is in an upper portion of said insulating layer and in the vicinity of the trench, said second conductive material extending toward said MOS transistor from said trench beyond a side portion of said trench and being in contact with a bottom surface of one of source/drain electrodes of said MOS transistor and with said first conductive material.

Claim 4

A semiconductor memory device comprising: a substrate formed on first semiconductor layer, said substrate comprising an insulating layer formed on said first semiconductor layer and a second semiconductor layer formed on said insulating layer; a shallow trench isolation structure formed in said substrate, wherein said shallow trench isolation structure extends through said second semiconductor layer and into said insulating layer of said substrate to thereby define an isolated active area of said second semiconductor layer; a MOS transistor formed on said active area; a trench located in the vicinity of said MOS transistor and reaching said first semiconductor layer through said second semiconductor layer and said insulating layer; a first conductive material filling in said trench; and a second conductive material formed in an etched portion of said insulating layer, which portion is in an upper portion of said insulating layer and in the vicinity of the trench, said second conductive material extending toward said MOS transistor from said trench beyond a side portion of said trench and being in contact with a bottom surface of one of source/drain electrodes of said MOS transistor and with said first conductive material.

Claim 5

A semiconductor memory device, comprising: a substrate formed on a first semiconductor layer, said substrate comprising an insulating layer formed on said first semiconductor layer, and a second semiconductor layer formed on said insulating layer; a shallow trench isolation structure formed in said substrate, wherein said shallow trench isolation structure extends through said second semiconductor layer and into said insulating layer of said substrate to thereby define an isolated active area of said second semiconductor layer; and a memory cell formed on said substrate, said memory cell comprising: a MOS transistor formed on said active area and comprising spaced apart source and drain regions formed in said second semiconductor layer and a gate electrode insulated from a channel region between said source and drain regions; a trench capacitor formed in a trench extending through said substrate and into said first semiconductor layer; an opening formed in a portion of the sidewall of said trench defined by said insulating layer, said opening extending outwardly from said trench to be under one of said source and drain regions of said MOS transistor; and a conductive material formed in said opening for electrically connecting said trench capacitor and said one of said source and drain regions.

Claim 6

A semiconductor memory device, comprising: a substrate formed on a first semiconductor layer, said substrate comprising an insulating layer formed on said first semiconductor layer, and a second semiconductor layer formed on said insulating layer; a shallow trench isolation structure formed in said substrate, wherein said shallow trench isolation structure extends through said second semiconductor layer and into said insulating layer of said substrate to thereby define an isolated active area of said second semiconductor layer; and a memory cell formed on said substrate, said memory cell comprising: a MOS transistor formed on said active area and comprising spaced apart source and drain regions formed in said second semiconductor layer and a gate electrode insulated from a channel region between said source and drain regions; a trench capacitor formed in a trench extending through said substrate and into said first semiconductor layer; an opening formed in a portion of the sidewall of said trench defined by said insulating layer, said opening extending outwardly from said trench to be under one of said source and drain regions of said MOS transistor; and a conductive material formed in said opening for electrically connecting said trench capacitor and said one of said source and drain regions.

Claim 7

The semiconductor memory device according to claim 3, wherein said insulating layer comprises a silicon dioxide layer.

Claim 8

The semiconductor memory device according to claim 3, wherein said conductive material connects an upper surface of said trench capacitor to a bottom surface of said one of said source and drain regions.

Claim 9

The semiconductor memory device according to claim 3, wherein said conductive material comprises polysilicon.

Claim 10

The semiconductor memory device according to claim 3, further comprising a shallow trench isolation structure for isolating said memory cell from other memory cells formed on said substrate.

Claim 11

A semiconductor memory device comprising: a substrate formed on a first semiconductor layer, said substrate comprising an insulating layer formed on said first semiconductor layer, and a second semiconductor layer formed on said insulating layer; a memory cell formed on said substrate; and a shallow trench isolation structure for isolating said memory cell from other memory cells formed on said substrate, said shallow trench isolation structure extending through said second semiconductor layer and into said insulating layer of said substrate to thereby define an isolated active area of said second semiconductor layer said memory cell comprising: a MOS transistor comprising spaced apart source and drain regions formed in said second semiconductor layer and a gate electrode insulated from a channel region between said source and drain regions; a trench capacitor formed in a trench extending through said substrate and into said first semiconductor layer; an opening formed in a portion of the sidewall of said trench defined by said insulating layer, said opening extending outwardly from said trench to be under one of said source and drain regions of said MOS transistor; and a conductive material formed in said opening for electrically connecting said trench capacitor and said one of said source and drain regions, wherein a depth of a trench of said shallow trench isolation structure beneath the surface of said substrate is greater than a depth of said opening beneath the surface of said substrate.

Claim 12

A semiconductor memory device comprising: a substrate formed on a first semiconductor layer, said substrate comprising an insulating layer formed on said first semiconductor layer, and a second semiconductor layer formed on said insulating layer; a memory cell formed on said substrate; and a shallow trench isolation structure for isolating said memory cell from other memory cells formed on said substrate, said shallow trench isolation structure extending through said second semiconductor layer and into said insulating layer of said substrate to thereby define an isolated active area of said second semiconductor layer said memory cell comprising: a MOS transistor comprising spaced apart source and drain regions formed in said second semiconductor layer and a gate electrode insulated from a channel region between said source and drain regions; a trench capacitor formed in a trench extending through said substrate and into said first semiconductor layer; an opening formed in a portion of the sidewall of said trench defined by said insulating layer, said opening extending outwardly from said trench to be under one of said source and drain regions of said MOS transistor; and a conductive material formed in said opening for electrically connecting said trench capacitor and said one of said source and drain regions, wherein a depth of a trench of said shallow trench isolation structure beneath the surface of said substrate is greater than a depth of said opening beneath the surface of said substrate.

Claim 13

A semiconductor memory device, comprising: a substrate formed on a first semiconductor layer, said substrate comprising an insulating layer formed on said first semiconductor layer, and a second semiconductor layer formed on said insulating layer; a shallow trench isolation structure formed in said substrate, wherein said shallow trench isolation structure and said insulating layer of said substrate define an active area of said second semiconductor layer; a memory cell formed on said substrate, said memory cell comprising: a MOS transistor formed on said active area and comprising spaced apart source and drain regions formed in said second semiconductor layer and a gate electrode insulated from a channel region between said source and drain region; and a trench capacitor formed in a trench extending through said substrate and into said first semiconductor layer; an opening formed in a portion of the sidewall of said trench defined by said insulating layer, said opening extending outwardly from said trench to be under one of said source and drain regions of said MOS transistor; and a conductive material formed in said opening for electrically connecting said trench capacitor and said one of said source and drain regions, wherein a depth of a trench of said shallow trench isolation structure beneath the surface of said substrate is less than a depth of said opening beneath the surface of said substrate.

Claim 14

A semiconductor memory device, comprising: a substrate formed on a first semiconductor layer, said substrate comprising an insulating layer formed on said first semiconductor layer, and a second semiconductor layer formed on said insulating layer; a shallow trench isolation structure formed in said substrate, wherein said shallow trench isolation structure and said insulating layer of said substrate define an active area of said second semiconductor layer; a memory cell formed on said substrate, said memory cell comprising: a MOS transistor formed on said active area and comprising spaced apart source and drain regions formed in said second semiconductor layer and a gate electrode insulated from a channel region between said source and drain region; and a trench capacitor formed in a trench extending through said substrate and into said first semiconductor layer; an opening formed in a portion of the sidewall of said trench defined by said insulating layer, said opening extending outwardly from said trench to be under one of said source and drain regions of said MOS transistor; and a conductive material formed in said opening for electrically connecting said trench capacitor and said one of said source and drain regions, wherein a depth of a trench of said shallow trench isolation structure beneath the surface of said substrate is less than a depth of said opening beneath the surface of said substrate.

Claim 15

A semiconductor memory device comprising: a first semiconductor layer; an insulating layer formed on a surface of said first semiconductor layer; a second semiconductor layer formed on a surface of said insulating layer; a shallow trench isolation structure which extends through said second semiconductor layer at least to the surface of said insulating layer on which said second semiconductor layer is formed, to thereby define an isolated active area of said second semiconductor layer; and a memory cell comprising: a MOS transistor formed on said active area and comprising spaced apart source and drain regions formed in said second semiconductor layer and a gate electrode insulated from a channel region between said source and drain regions; and a trench capacitor formed in a trench extending through said second semiconductor layer and said insulating layer and into said first semiconductor layer, said trench capacitor electrically connected to said MOS transistor, said trench capacitor comprising a dielectric layer having a uniform thickness formed on walls of said trench and a conductive layer formed on said dielectric layer; an opening extending outwardly from said trench in which said trench capacitor is formed to be under one of said source and drain regions of said MOS transistor; and a conductive material formed in said opening for providing the electrical connection between said trench capacitor and said MOS transistor.

Claim 16

A semiconductor memory device comprising: a first semiconductor layer; an insulating layer formed on a surface of said first semiconductor layer; a second semiconductor layer formed on a surface of said insulating layer; a shallow trench isolation structure which extends through said second semiconductor layer at least to the surface of said insulating layer on which said second semiconductor layer is formed, to thereby define an isolated active area of said second semiconductor layer; and a memory cell comprising: a MOS transistor formed on said active area and comprising spaced apart source and drain regions formed in said second semiconductor layer and a gate electrode insulated from a channel region between said source and drain regions; and a trench capacitor formed in a trench extending through said second semiconductor layer and said insulating layer and into said first semiconductor layer, said trench capacitor electrically connected to said MOS transistor, said trench capacitor comprising a dielectric layer having a uniform thickness formed on walls of said trench and a conductive layer formed on said dielectric layer; an opening extending outwardly from said trench in which said trench capacitor is formed to be under one of said source and drain regions of said MOS transistor; and a conductive material formed in said opening for providing the electrical connection between said trench capacitor and said MOS transistor.

Claim 17

A semiconductor memory device comprising: a semiconductor layer; an insulating layer formed on a surface of said semiconductor layer; an active area of an island shape formed on a surface of said insulating layer; a memory cell comprising: a MOS transistor formed on said active area and comprising spaced apart source and drain regions formed in said active area and a gate electrode insulated from a channel region between said source and drain regions; and a trench capacitor formed in a trench extending through said active area and said insulating layer and into said semiconductor layer, said trench capacitor comprising a dielectric layer formed on an inner surface of a portion of said trench which is formed in said semiconductor layer and a conductive layer formed on said dielectric layer; an opening extending outwardly from said trench in which said trench capacitor is formed to be under one of said source and drain regions of said MOS transistor; and a conductive material formed in said opening for providing the electrical connection between said trench capacitor and said MOS transistor, wherein said active area is physically isolated from all other active areas.

Claim 18

A semiconductor memory device comprising: a semiconductor layer; an insulating layer formed on a surface of said semiconductor layer; an active area of an island shape formed on a surface of said insulating layer; a memory cell comprising: a MOS transistor formed on said active area and comprising spaced apart source and drain regions formed in said active area and a gate electrode insulated from a channel region between said source and drain regions; and a trench capacitor formed in a trench extending through said active area and said insulating layer and into said semiconductor layer, said trench capacitor comprising a dielectric layer formed on an inner surface of a portion of said trench which is formed in said semiconductor layer and a conductive layer formed on said dielectric layer; an opening extending outwardly from said trench in which said trench capacitor is formed to be under one of said source and drain regions of said MOS transistor; and a conductive material formed in said opening for providing the electrical connection between said trench capacitor and said MOS transistor, wherein said active area is physically isolated from all other active areas.

Claim 19

A semiconductor memory device comprising: a semiconductor layer; an insulating layer formed on a surface of said semiconductor layer; an active area of an island shape formed on a surface of said insulating layer; a memory cell comprising: a MOS transistor formed on said active area and comprising spaced apart source and drain regions formed in said active area and a gate electrode insulated from a channel region between said source and drain regions; and a trench capacitor formed in a trench extending through said active area and said insulating layer and into said semiconductor layer; an opening extending outwardly from said trench in which said trench capacitor is formed to be under one of said source and drain regions of said MOS transistor; and a conductive material formed in said opening for providing the electrical connection between said trench capacitor and said MOS transistor, wherein said active area is physically isolated from all other active areas.

Claim 20

A semiconductor memory device comprising: a semiconductor layer; an insulating layer formed on a surface of said semiconductor layer; an active area of an island shape formed on a surface of said insulating layer; a memory cell comprising: a MOS transistor formed on said active area and comprising spaced apart source and drain regions formed in said active area and a gate electrode insulated from a channel region between said source and drain regions; and a trench capacitor formed in a trench extending through said active area and said insulating layer and into said semiconductor layer; an opening extending outwardly from said trench in which said trench capacitor is formed to be under one of said source and drain regions of said MOS transistor; and a conductive material formed in said opening for providing the electrical connection between said trench capacitor and said MOS transistor, wherein said active area is physically isolated from all other active areas.

Claim 21

A semiconductor memory device comprising: a semiconductor layer; an insulating layer formed on a surface of said semiconductor layer; an active area of an island shape formed on a surface of said insulating layer and physically isolated from a surrounding thereof; a memory cell comprising: a MOS transistor formed on said active area and comprising spaced apart source and drain regions formed in said active area and a gate electrode insulated from a channel region between said source and drain regions; and a trench capacitor formed in a trench extending through said active area and said insulating layer and into said semiconductor layer, said trench capacitor comprising a dielectric layer formed on an inner surface of a portion of said trench which is formed in said semiconductor layer and a conductive layer formed on said dielectric layer; an opening extending outwardly from said trench in which said trench capacitor is formed to be under one of said source and drain regions of said MOS transistor; and a conductive material formed in said opening for providing the electrical connection between said trench capacitor and said MOS transistor.

Claim 22

A semiconductor memory device comprising: a semiconductor layer; an insulating layer formed on a surface of said semiconductor layer; an active area of an island shape formed on a surface of said insulating layer and physically isolated from a surrounding thereof; a memory cell comprising: a MOS transistor formed on said active area and comprising spaced apart source and drain regions formed in said active area and a gate electrode insulated from a channel region between said source and drain regions; and a trench capacitor formed in a trench extending through said active area and said insulating layer and into said semiconductor layer, said trench capacitor comprising a dielectric layer formed on an inner surface of a portion of said trench which is formed in said semiconductor layer and a conductive layer formed on said dielectric layer; an opening extending outwardly from said trench in which said trench capacitor is formed to be under one of said source and drain regions of said MOS transistor; and a conductive material formed in said opening for providing the electrical connection between said trench capacitor and said MOS transistor.

Claim 23

A semiconductor memory device comprising: a semiconductor layer; an insulating layer formed on a surface of said semiconductor layer; an active area of an island shape formed on a surface of said insulating layer and physically isolated from a surrounding thereof; a memory cell comprising: a MOS transistor formed on said active area and comprising spaced apart source and drain regions formed in said active area and a gate electrode insulated from a channel region between said source and drain regions; and a trench capacitor formed in a trench extending through said active area and said insulating layer and into said semiconductor layer; an opening extending outwardly from said trench in which said trench capacitor is formed to be under one of said source and drain regions of said MOS transistor; and a conductive material formed in said opening for providing the electrical connection between said trench capacitor and said MOS transistor.

Claim 24

A semiconductor memory device comprising: a semiconductor layer; an insulating layer formed on a surface of said semiconductor layer; an active area of an island shape formed on a surface of said insulating layer and physically isolated from a surrounding thereof; a memory cell comprising: a MOS transistor formed on said active area and comprising spaced apart source and drain regions formed in said active area and a gate electrode insulated from a channel region between said source and drain regions; and a trench capacitor formed in a trench extending through said active area and said insulating layer and into said semiconductor layer; an opening extending outwardly from said trench in which said trench capacitor is formed to be under one of said source and drain regions of said MOS transistor; and a conductive material formed in said opening for providing the electrical connection between said trench capacitor and said MOS transistor.