US6169701B1
Expired / Lapsed
US
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Semiconductor memory device using shared sense amplifier system
Assignee: Socionext Inc
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Filing: 1997-10-07
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Granted: 2001-01-02
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Expires: 2017-10-07
Abstract
Abstract In the present invention, the gate electrodes of the bit line transfer gates for bit line pair selection that perform connection and isolation of the sense amplifiers and bit line pairs are put into floating condition during activation of the sense amplifier in the active period. Thus, a system is adopted according to which the potential of the bit line is driven to power source voltage Vcc or high voltage corresponding thereto by the sense amplifier in the active condition, the pre-charging potential of the bit line pair being made lower than half the power source voltage Vcc, for example ground potential Vss. Thanks to the amplification action of the sense amplifier, by utilising the fact that one side of the plurality of bit line pairs is inevitably driven from low potential to the power source voltage Vcc level or high voltage corresponding thereto, the potential of the gate electrodes which are in floating condition is boosted higher due to capacitative coupling, enabling the potential of the bit line on rewriting to be boosted to a voltage driven by the sense amplifier, for example power source voltage.
Inventors
- 👤 Satoshi Eto
- 👤 Masato Matsumiya
- 👤 Hideki Kanou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:09
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/065
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
196 words
A semiconductor memory device comprising: first and second memory cell arrays comprising a plurality of word lines, a plurality of bit line pairs intersecting thereto, and memory cells provided at intersections therebetween; a pre-charging circuit that drives the bit line pairs together to a first potential in a pre-charging period; a row of sense amplifiers, arranged between the first and second memory cell arrays, in an active period, detecting potential differences between said bit line pairs and driving ones of said bit line pairs to a second potential higher than the first potential; first bit line transfer gates respectively arranged between the bit line pairs in the first memory cell array and the sense amplifiers, conducting when the first memory cell array is selected; second bit line transfer gates respectively arranged between the bit line pairs in the second memory cell array and the sense amplifiers, conducting when second memory cell array is selected; and a bit line transfer gate drive circuit which puts the gate electrodes of the first or second bit line transfer gates into floating condition in the active period, in response to a selection of the first or second memory cell array.
Claim 2
Dependent Claim
196 words
A semiconductor memory device comprising: first and second memory cell arrays comprising a plurality of word lines, a plurality of bit line pairs intersecting thereto, and memory cells provided at intersections therebetween; a pre-charging circuit that drives the bit line pairs together to a first potential in a pre-charging period; a row of sense amplifiers, arranged between the first and second memory cell arrays, in an active period, detecting potential differences between said bit line pairs and driving ones of said bit line pairs to a second potential higher than the first potential; first bit line transfer gates respectively arranged between the bit line pairs in the first memory cell array and the sense amplifiers, conducting when the first memory cell array is selected; second bit line transfer gates respectively arranged between the bit line pairs in the second memory cell array and the sense amplifiers, conducting when second memory cell array is selected; and a bit line transfer gate drive circuit which puts the gate electrodes of the first or second bit line transfer gates into floating condition in the active period, in response to a selection of the first or second memory cell array.
Claim 3
Dependent Claim
22 words
The semiconductor memory device according to claim 1 wherein the first potential is a potential lower than half a power source voltage.
Claim 4
Dependent Claim
23 words
The semiconductor memory device according to claim 2 wherein the second potential is a potential about the same as the power source voltage.
Claim 5
Dependent Claim
75 words
The semiconductor memory device according to claim 1 wherein the bit line transfer gate drive circuit makes the first and second bit line transfer gates conductive in the pre-charging period, and in the active period, the bit line transfer gate drive circuit makes one of the first and second bit line transfer gates non-conductive, and puts the gate electrodes of the other of the first and second bit line transfer gates into the floating condition.
Claim 6
Dependent Claim
71 words
The semiconductor memory device according to claim 1 wherein predetermined coupling capacitances are provided between the gate electrodes of the first and second bit line transfer gates and the corresponding bit line pairs; and in the active period, on amplifying the potential differences between said bit line, through the coupling capacitances, potential at the gate electrodes that are in the floating condition are boosted into a power source voltage or more.
Claim 7
Dependent Claim
221 words
A semiconductor memory device comprising: first and second memory cell arrays comprising a plurality of word lines, a plurality of bit line pairs intersecting thereto, and memory cells provided at intersections therebetween; a pre-charging circuit that drives the bit line pairs together to a first potential in a pre-charging period; a row of sense amplifiers, arranged between the first and second memory cell arrays, in an active period, detecting potential differences between said bit line pairs and driving ones of said bit line pairs to a second potential higher than the first potential; first bit line transfer gates respectively arranged between the bit line pairs in the first memory cell array and the sense amplifiers, conducting when the first memory cell array is selected; second bit line transfer gates respectively arranged between the bit line pairs in the second memory cell array and the sense amplifiers, conducting when the second memory cell array is selected; and a bit line transfer gate drive circuit which makes the first and second bit line transfer gates conductive in the pre-charging period, and, in the active period, the bit line transfer gate drive circuit puts gate electrodes of ones of the first and second bit line transfer gates into floating condition, and makes the other of the first and second bit line transfer gates non-conductive.
Claim 8
Dependent Claim
221 words
A semiconductor memory device comprising: first and second memory cell arrays comprising a plurality of word lines, a plurality of bit line pairs intersecting thereto, and memory cells provided at intersections therebetween; a pre-charging circuit that drives the bit line pairs together to a first potential in a pre-charging period; a row of sense amplifiers, arranged between the first and second memory cell arrays, in an active period, detecting potential differences between said bit line pairs and driving ones of said bit line pairs to a second potential higher than the first potential; first bit line transfer gates respectively arranged between the bit line pairs in the first memory cell array and the sense amplifiers, conducting when the first memory cell array is selected; second bit line transfer gates respectively arranged between the bit line pairs in the second memory cell array and the sense amplifiers, conducting when the second memory cell array is selected; and a bit line transfer gate drive circuit which makes the first and second bit line transfer gates conductive in the pre-charging period, and, in the active period, the bit line transfer gate drive circuit puts gate electrodes of ones of the first and second bit line transfer gates into floating condition, and makes the other of the first and second bit line transfer gates non-conductive.
Claim 9
Dependent Claim
132 words
A semiconductor memory device comprising: bit line pair; memory cells each connected to either of the bit line pair; a pre-charging circuit that pre-charges the bit line pair together to a first potential in a pre-charging period; a sense amplifier, operatively connected to said bit line pair, in an active period, detecting a potential difference of the bit line pair and driving one of said bit line pair to a second potential higher than the first potential; a pair of bit line transfer gates each arranged between one of the bit line pair and the sense amplifier; and a bit line transfer gate drive circuit which puts gate electrodes of the pair of bit line transfer gates into floating condition in the active period wherein one of the memory cells is selected.
Claim 10
Dependent Claim
132 words
A semiconductor memory device comprising: bit line pair; memory cells each connected to either of the bit line pair; a pre-charging circuit that pre-charges the bit line pair together to a first potential in a pre-charging period; a sense amplifier, operatively connected to said bit line pair, in an active period, detecting a potential difference of the bit line pair and driving one of said bit line pair to a second potential higher than the first potential; a pair of bit line transfer gates each arranged between one of the bit line pair and the sense amplifier; and a bit line transfer gate drive circuit which puts gate electrodes of the pair of bit line transfer gates into floating condition in the active period wherein one of the memory cells is selected.
Claim 11
Independent Claim
101 words
A method for operating a semiconductor memory device having memory cells connected to a bit line and a transfer gate transistor disposed between the bit line and a sense amplifier, comprising steps of: pre-charging the bit line to a first potential; setting a potential at a gate electrode of the transfer gate transistor to a second potential higher than the first potential, then putting the gate electrode into floating condition wherein one of one of the memory cells in selected; and activating the sense amplifier, thereby the potential at the gate electrode being self-boosted and becoming higher than the second potential.
Claim 12
Independent Claim
101 words
A method for operating a semiconductor memory device having memory cells connected to a bit line and a transfer gate transistor disposed between the bit line and a sense amplifier, comprising steps of: pre-charging the bit line to a first potential; setting a potential at a gate electrode of the transfer gate transistor to a second potential higher than the first potential, then putting the gate electrode into floating condition wherein one of one of the memory cells in selected; and activating the sense amplifier, thereby the potential at the gate electrode being self-boosted and becoming higher than the second potential.
References Cited (Backward Citations)
US5243574A
Cited
US5740113A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-02 | 2004-07-03 | 2005-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-02 | 2008-07-03 | 2009-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-02 | 2012-07-03 | 2013-01-02 | $7700.00 | Window Closed / Lapsed |