US6174758B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor chip having fieldless array with salicide gates and methods for making same
Assignee: Tower Semiconductor Ltd
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Filing: 1999-03-03
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Granted: 2001-01-16
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Expires: 2019-03-03
Abstract
Abstract A semiconductor process, which creates a semiconductor devices that includes logic transistors fabricated in a first region and a fieldless array fabricated in a second region, is provided. Both the logic transistors and the fieldless array transistors have gates comprising a polysilicon layer with a silicide layer. The logic transistors have self-aligned silicide regions formed on their source and drain regions. Self-aligned silicide regions are not formed on the source and drain regions of the fieldless array transistors, thereby preventing undesirable electrical shorts which could otherwise occur within the fieldless array. The silicide structures can be fabricated by depositing polysilicon over the first and second regions, etching the polysilicon layer in the first region to define gates of the logic transistors, depositing and reacting a refractory metal, removing the non-reacted refractory metal, and then patterning the polysilicon and silicide in the second region to define gates of the fieldless array transistors.
Inventors
- 👤 Ishai Nachumovsky
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:34
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0128; H10D84/0135; H10D84/0137; H10D84/02; H10D84/03; H10D84/038; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0128; H10W10/10; H10W10/13
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
93 words
A method for forming a semiconductor device having a first region and a second region, said method comprising the steps of: forming a polysilicon layer over said first region and said second region; etching a first portion of said polysilicon layer over said first region to form a first polysilicon gate structure for a logic transistor in a logic transistor etching step; and etching a second portion of said polysilicon layer over said second region to form a second polysilicon gate structure for a fieldless array transistors in a fieldless array etching step.
Claim 2
Independent Claim
93 words
A method for forming a semiconductor device having a first region and a second region, said method comprising the steps of: forming a polysilicon layer over said first region and said second region; etching a first portion of said polysilicon layer over said first region to form a first polysilicon gate structure for a logic transistor in a logic transistor etching step; and etching a second portion of said polysilicon layer over said second region to form a second polysilicon gate structure for a fieldless array transistors in a fieldless array etching step.
Claim 3
Dependent Claim
50 words
The method of claim 1 , further comprising the steps of: depositing a metal layer over said polysilicon layer prior to said step of etching said polysilicon layer over said second region; and silicidizing said metal layer to form a silicide layer where said metal layer contacts said polysilicon layer.
Claim 4
Dependent Claim
25 words
The method of claim 2 , further comprising the step of silicidizing said silicide layer to reduce a silicide sheet resistance of said silicide layer.
Claim 5
Dependent Claim
33 words
The method of claim 1 , wherein said first region of said semiconductor device comprises field oxide and said second portion of said semiconductor device comprises a fieldless array of fieldless array transistors.
Claim 6
Dependent Claim
19 words
The method of claim 1 , further comprising the step of depositing a photoresist layer over said polysilicon layer.
Claim 7
Dependent Claim
21 words
The method of claim 5 , further comprising the step of developing and exposing said photoresist layer over said first region.
Claim 8
Dependent Claim
17 words
The method of claim 1 , further comprising the step of implanting impurities into said semiconductor device.
Claim 9
Dependent Claim
41 words
The method of claim 1 , further comprising the steps of: creating a first dielectric layer on said semiconductor device; depositing a floating gate layer on said first dielectric layer; and creating a second dielectric layer on said floating gate layer.
Claim 10
Dependent Claim
28 words
The method of claim 8 , wherein said step of creating a first dielectric layer on said semiconductor device comprises oxidizing an upper surface of said semiconductor device.
Claim 11
Dependent Claim
30 words
The method of claim 8 , wherein said step of creating a second dielectric layer on said floating gate layer comprises oxidizing an upper surface of said floating gate layer.
Claim 12
Dependent Claim
13 words
The method of claim 8 , wherein said floating gate layer is nitride.
Claim 13
Dependent Claim
19 words
The method of claim 1 , further comprising the step of forming buried bit lines in said second region.
Claim 14
Dependent Claim
49 words
The method of claim 12 , wherein said step of forming a plurality of buried bit lines in said second region comprises the steps of: implanting said plurality of bit lines using ion implantation; and creating a plurality of bit line oxide overlying said plurality of buried bit lines.
Claim 15
Dependent Claim
28 words
The method of claim 1 , further comprising the steps of: forming a source region in said first region; and forming a drain region in said first region.
Claim 16
Dependent Claim
21 words
The method of claim 14 , further comprising the step of forming a plurality of oxide spacers in said first region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2004-01-16 | 2004-07-17 | 2005-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-16 | 2008-07-17 | 2009-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-16 | 2012-07-17 | 2013-01-16 | $7700.00 | Window Closed / Lapsed |