Semiconductor memory device

Claim 2

A semiconductor memory device having a memory cell, comprising: a write transistor with a gate connected to a write word line and with a first impurity region forming a source or drain connected to a bit line; a read transistor with a gate connected to a second impurity region forming a source or drain of the write transistor, a first impurity region connected to a read word line, and a second impurity region connected to a bit line; and a capacitor connected between the gate and the first impurity region of the read transistor.

Claim 3

A semiconductor memory device as set forth in claim 1 , wherein the capacitor includes a parasitic capacitance in said read transistor.

Claim 4

A semiconductor memory device as set forth in claim 1 , wherein the capacitor includes: a parasitic capacitance inside the read transistor; and an external capacitance element connected to the outside of said read transistor.

Claim 5

A semiconductor memory device as set forth in claim 2 , wherein said read word line includes an impurity region formed in a surface region of a semiconductor substrate or a semiconductor layer supported on a substrate; and said parasitic capacitance of the read transistor is formed at a portion where a gate electrode formed on a gate insulating film overlaps the first impurity region branched from an impurity region which is or is connectable to said read word line.

Claim 6

A semiconductor memory device as set forth in claim 4 , wherein, in said read transistor, the area of the overlap portion between the first impurity region and the gate electrode where said parasitic capacitance is formed is larger than the area of the overlap portion between the second impurity region and gate electrode.

Claim 7

A semiconductor memory device as set forth in claim 3 , wherein said read word line includes an impurity region formed in the surface region of a semiconductor substrate or a semiconductor layer supported on a substrate and passing between the memory cells; a gate electrode of said read transistor extends, on a gate insulating film, from the above of a channel forming region between said first and second impurity regions to the above of the impurity region which is or is connectable to the read word line; said parasitic capacitance is formed at a portion where the gate electrode of the read transistor overlaps the first impurity region thereof branched from said impurity region which is or is connectable to the read word line; and said external capacitance element is formed at a portion the gate electrode of the read transistor overlaps said impurity region which is or is connectable to the read word line.

Claim 8

A semiconductor memory device as set forth in claim 6 , wherein said gate electrode of the read transistor intersects the straight portion of said impurity region which is or is connectable to the read word line avoiding the branching portion of the first impurity region of the read transistor from said impurity region which is or is connectable to said read word line.

Claim 9

A semiconductor memory device as set forth in claim 7 , wherein, in said read transistor, the area of the overlap portion between the first impurity region and the gate electrode where said parasitic capacitance is formed is equal to the area of the overlap portion between the second impurity region and the gate electrode.

Claim 10

A semiconductor memory device as set forth in claim 3 , wherein said read word line includes: an impurity region formed in the surface region of a semiconductor substrate or a semiconductor layer supported by a substrate and passing between memory cells; and an upper interconnection layer electrically connected to said impurity region, wherein a gate electrode of said read transistor extends, on a gate insulating film, from the above of a channel forming region between said first and second impurity regions to the above of said impurity region which is or is connectable to said read word line; said parasitic capacitance is formed at a portion where the gate electrode of the read transistor overlaps the first impurity region thereof branched from said impurity region which is or is connectable to the read word line; and said external capacitance element includes: a first capacitance element formed at a portion where said gate electrode of the read transistor exists on a gate insulating film and overlaps said impurity region which is or is connectable to the read word line; and a second capacitance element formed at a portion where said gate electrode of the read transistor exists on an insulating film and overlaps the further higher interconnection layer.

Claim 11

A semiconductor memory device as set forth in claim 1 , further comprising: a write control circuit for holding said bit line at a voltage corresponding to a write data, applying a write voltage to said write word line to turn on said write transistor, transmitting a voltage corresponding to the held voltage of said bit line to a gate of said read transistor and having it held there at the time of a write operation; and a read control circuit for applying a read voltage to said read word line and controlling the on or off state of the read transistor in accordance with the held voltage held at the gate of the read transistor at the time of a read operation.

Claim 12

A semiconductor memory device as set forth in claim 10 , further comprising a discharge circuit connected to said bit line and discharging the bit line to a reference potential at the time of start of said read operation.

Claim 13

A semiconductor memory device as set forth in claim 11 , wherein said bit line is held in a floating state after being discharged by said discharge circuit.

Claim 14

A semiconductor memory device as set forth in claim 10 , wherein a high level or low level held voltage held at the gate of said read transistor corresponding to the write data is set lower than a threshold voltage of the read transistor.

Claim 15

A semiconductor memory device as set forth in claim 10 , wherein when said read voltage is applied to said read word line at the time of read operation, the potential of the gate of the read transistor is boosted by a capacitive coupling produced through said capacitor formed with said first impurity region, when a held voltage of the gate of the read transistor is a high level that read transistor is turned on, and when the held voltage of the gate of the read transistor is a low level that read transistor is off.

Claim 16

A semiconductor memory device as set forth in claim 1 , comprising a first memory cell and a second memory cell with gates of write transistors connected to a common write word line and said bit line includes: a first bit line with the write transistor of said first memory cell and the read transistor of said second memory cell connected to it; and a second bit line with the read transistor of said first memory cell and the write transistor of said second memory cell connected to it.

Claim 17

A semiconductor memory device as set forth in claim 1 , wherein: memory cells are arranged in an m×n array (m, n: any natural numbers), said write word line, said read word line, and said bit line are each connected in common between memory cells in the row direction or column direction, and wherein said semiconductor memory device further comprises: a write control circuit for holding said bit line at a voltage corresponding to a write data, applying a write voltage to said write word line to turn on said write transistor, transmitting a voltage corresponding to the held voltage of said bit line to a gate of said read transistor and having it held there at the time of a write operation; a read control circuit for applying a read voltage to said read word line and controlling the on or off state of the read transistor in accordance with the held voltage held at the gate of the read transistor at the time of a read operation; a discharge circuit connected to said bit line and discharging the bit line to a reference potential at the time of start of the read operation; and a sense amplifier connected to said bit line and detecting a voltage of the bit line at the time of read operation.

Claim 18

A semiconductor memory device as set forth in claim 16 , wherein a reference memory cell connected to a reference bit line are connected for said bit line and said reference memory cell further comprises: a reference write transistor with a gate connected to a reference write word line and a first impurity region forming a source or drain connected to said reference bit line; a reference read transistor with a gate connected to a second impurity region forming a source or drain of said reference write transistor, a first impurity region connected to a reference read word line, and a second impurity region connected to a reference bit line; and a reference capacitor connected between the gate and the first impurity region of said reference read transistor.

Claim 19

A semiconductor memory device as set forth in claim 17 , further comprising a reference data write circuit for writing predetermined storage data in said reference memory cell.

Claim 20

A semiconductor memory device as set forth in claim 17 , wherein said discharge circuit discharges the bit line and the corresponding reference bit line to the reference voltage before reading.

Claim 21

A semiconductor memory device as set forth in claim 17 , wherein said sense amplifier detects a potential difference between said bit line and said reference bit line and amplifies said detected potential difference.