← Back to Patent Explorer
US6323671B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Charge gain stress test circuit for nonvolatile memory and test method using the same

Assignee: SK Hynix Inc
•
Filing: 1999-04-15
•
Granted: 2001-11-27
•
Expires: 2019-04-15
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A charge gain stress test circuit for a nonvolatile memory and a test method using the same according to the present invention allow a maximum size of a voltage used for a stress lower than a voltage applied in a normal operation. The preferred embodiment sufficiently increases an absolute value of an applicable stress voltage by using a reference current to control a stress voltage value without burdening the peripheral circuits. The preferred embodiment optimizes a stress time, namely the test time.

Inventors

  • 👤 Kyeong-Man Ra

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 17:57
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C29/00; G11C29/04; G11C29/50; G11C16/04; G11C2029/5006

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 162 words
A circuit for performing a -charge gain stress test for a nonvolatile memory having plurality of cells, comprising: a reference current generator that generates a reference current; a comparator that compares a cell current from a selected one of the nonvolatile memory cells with the reference current and outputting a compare result; a first switch controlled by a first control signal to selectively connect the comparator or a first voltage to a drain of the selected nonvolatile memory cell; a second switch controlled by the first control signal to selectively connect the first voltage or a second voltage to a gate of the selected nonvolatile memory cell, or controlled by a second control signal to selectively connect the first voltage or a third voltage to the gate of the selected nonvolatile memory cell; and a third switch controlled by the second control signal to selectively connect the first voltage or a fourth voltage to a source of the selected nonvolatile memory cell.
Claim 2
Dependent Claim 162 words
A circuit for performing a -charge gain stress test for a nonvolatile memory having plurality of cells, comprising: a reference current generator that generates a reference current; a comparator that compares a cell current from a selected one of the nonvolatile memory cells with the reference current and outputting a compare result; a first switch controlled by a first control signal to selectively connect the comparator or a first voltage to a drain of the selected nonvolatile memory cell; a second switch controlled by the first control signal to selectively connect the first voltage or a second voltage to a gate of the selected nonvolatile memory cell, or controlled by a second control signal to selectively connect the first voltage or a third voltage to the gate of the selected nonvolatile memory cell; and a third switch controlled by the second control signal to selectively connect the first voltage or a fourth voltage to a source of the selected nonvolatile memory cell.
Claim 3
Dependent Claim 15 words
The circuit of claim 1 , wherein the first voltage is a ground source voltage.
Claim 4
Dependent Claim 21 words
The circuit of claim 1 , wherein the second voltage is used for applying a stress to the nonvolatile memory cell.
Claim 5
Dependent Claim 20 words
The circuit of claim 1 , wherein the third voltage is used for erasing data of the nonvolatile memory cell.
Claim 6
Dependent Claim 20 words
The circuit of claim 1 , wherein the fourth voltage is used for erasing data of the nonvolatile memory cell.
Claim 7
Dependent Claim 13 words
The circuit of claim 1 , wherein said comparator is a sense amp.
Claim 8
Dependent Claim 16 words
The circuit of claim 1 , wherein the nonvolatile memory cell is a flash memory cell.

References Cited (Backward Citations)

US5745412A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-11-26 2005-05-28 2005-11-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2008-11-26 2009-05-28 2009-11-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2012-11-26 2013-05-28 2013-11-27 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag