Method and apparatus for a Gigabit Ethernet MAC (GMAC)

Claim 2

Adapted for communication with an input/output (I/O) device, a media access controller comprising; a first transceiver having a first receiver and a first transmitter, the first transceiver being configured to send and receive data from a destination port; a second transceiver having a second receiver and a second transmitter, the second transceiver being configured to send and receive data from the destination port; wherein said first transceiver and said second transceiver establish a first physical link and a second physical link with the destination port such that if one of said first physical link and said second physical link is active and a link interruption occurs said media access controller may switch to the other of said first physical link and said second physical link as a backup link; and a CPU interface for providing interrupts to at least one of the first receiver and the second receiver in response selectable status events including the link interruption and failure of the I/O device.

Claim 3

The media access controller as described in claim 1 wherein said first receiver and said second receiver receive data from an I/O device over said first and second physical links respectively.

Claim 4

The media access controller as described in claim 1 wherein said first transmitter and said second transmitter transmit signals to an I/O device over said first and second physical links respectively and wherein data packets are transmitted over said active link and idle code is transmitted over said backup link.

Claim 5

The media access controller as described in claim 1 further comprising: a receiver output for outputting data to a port interface device.

Claim 6

The media access controller as described in claim 1 further comprising: a transmit input for accepting data from a port interface device.

Claim 7

The media access controller as described in claim 1 further comprising: a first clock domain at said first transceiver; and a second clock domain at said second transceiver.

Claim 8

The media access controller as described in claim 5 further comprising: a third clock domain at said transmit input.

Claim 9

The media access controller as described in claim 1 further comprising: a fourth clock domain for driving the remaining internal workings of said media access controller.

Claim 10

The media access controller as described in claim 1 further comprising: a first FIFO coupled to said first and second transceivers for passing data packets from said active link and discarding data from said backup link.

Claim 11

Adapted for communication with an input/output (I/O) device over a link, a media access controller comprising: a first transceiver having a first receive bus interface (RXIN-A) and a first transmit bus interface (TXOUT-A), the first transceiver configured to receive and send a data to the I/O device; a second transceiver having a second receive bus interface (RXIN-B) and a second transmit bus interface (TXOUT-B), the second transceiver configured to receive and send data from the I/O device; wherein one of said first and second transceivers acts as a primary transceiver and the other of said first and second transceivers acts as a backup transceiver, said primary transceiver is capable of being switched to an off-line status and said backup transceiver is capable of being switched to an on-line status when an interrupt occurs; a CPU interface for providing interrupts to at least one receiver of said first and second transceivers in response to selectable status events including a failure of the link or a configuration change of the I/O device; a receiver output for transmitting data to a port interface device; and a transmit input (TXIN) for accepting packet data from a port interface device.

Claim 12

Adapted for communication with an input/output (I/O) device over a link, a media access controller comprising: a first transceiver having a first receive bus interface (RXIN-A) and a first transmit bus interface (TXOUT-A), the first transceiver configured to receive and send a data to the I/O device; a second transceiver having a second receive bus interface (RXIN-B) and a second transmit bus interface (TXOUT-B), the second transceiver configured to receive and send data from the I/O device; wherein one of said first and second transceivers acts as a primary transceiver and the other of said first and second transceivers acts as a backup transceiver, said primary transceiver is capable of being switched to an off-line status and said backup transceiver is capable of being switched to an on-line status when an interrupt occurs; a CPU interface for providing interrupts to at least one receiver of said first and second transceivers in response to selectable status events including a failure of the link or a configuration change of the I/O device; a receiver output for transmitting data to a port interface device; and a transmit input (TXIN) for accepting packet data from a port interface device.

Claim 13

The media access controller as described in claim 10 wherein said first receive bus interface and said second receive bus interface accept data from the I/O device over a first physical link and a second physical link respectively.

Claim 14

The media access controller as described in claim 10 wherein said first transmit bus interface and said second transmit bus interface send signals to the I/O device over a first physical link and a second physical link respectively.

Claim 15

The media access controller as described in claim 12 wherein said transmit bus interface of said primary transceiver sends data packets to said I/O device and said transmit bus interface of said backup transceiver send idle code to said I/O device.

Claim 16

The media access controller as described in claim 10 further comprising a first clock domain at said first transceiver; and a second clock domain at said second transceiver. a third clock domain at said transmit input. a fourth clock domain for driving the remaining internal workings of said media access controller.

Claim 17

The media access controller as described in claim 14 further comprising a first FIFO for adjusting frequency and phase differences between said first clock domain and said fourth clock domain and between said second clock domain and said fourth clock domain.

Claim 18

The media access controller as described in claim 14 further comprising a second FIFO for crossing from said third clock domain at said transmit input to said fourth clock domain driving said internal workings of said media access controller.

Claim 21

The method as described in claim 17 wherein said first and second links are created by said first transceiver and said second transceiver in a single media access controller.

Claim 22

The method as described in claim 17 wherein one of said first link and said second link is chosen as a primary link and the other of said first link and said second link is a backup link.

Claim 23

The method as described in claim 19 wherein signals are transmitted to an I/O device over said first and second links, data signals are transmitted over said primary link and idle code signals are transmitted over said backup link.

Claim 24

The method as described in claim 17 wherein the logic is a central processing unit.

Claim 25

The method as described in claim 19 wherein the error event further includes a configuration change in which the I/O device determines to switch a flow of data from the primary link to said backup link.