Efficient memory management for channel drivers in next generation I/O system

Claim 2

A memory manager to manage virtual memory corresponding to a channel driver, comprising: a plurality of memory elements to enable translation of virtual memory addresses associated with the channel driver to physical memory locations, said plurality of memory elements being grouped to include at least first and second memory element configurations, said at least first and second memory element configurations separately processing allocated memory elements and unused memory elements, respectively.

Claim 3

The memory manager of claim 1 , wherein said first memory element configuration holds used or allocated memory elements in a hashed table configuration.

Claim 4

The memory manager of claim 1 , wherein said second memory element configuration holds unused memory elements in a circularly linked-list configuration.

Claim 5

A memory management system comprising: a pool of memory entries having at least first and second sub-pools being configured such that the first sub-pool includes unused memory entries and the second sub-pool includes allocated memory entries; and a memory manager to reserve and process said pool of memory entries, said memory manager translating virtual memory allocated by said pool of memory entries to physical memory locations.

Claim 6

A memory management system comprising: a pool of memory entries having at least first and second sub-pools being configured such that the first sub-pool includes unused memory entries and the second sub-pool includes allocated memory entries; and a memory manager to reserve and process said pool of memory entries, said memory manager translating virtual memory allocated by said pool of memory entries to physical memory locations.

Claim 7

The system of claim 4 , wherein an entry of said pool of memory entries includes at least three elements.

Claim 8

The system of claim 5 , wherein a first element of said at least three elements is a start index indicating a first entry in the pool, a second element is a number of contiguous entries available, and a third element is a pointer to a next entry in the pool.

Claim 9

The system of claim 4 , wherein said first sub-pool is a circularly linked-list.

Claim 10

The system of claim 7 , wherein said circularly linked-list has a head pointer indicating a first entry in the list, a tail pointer indicating a last entry in the list, and a next pointer used as a starting point for searches to find first available block of entries.

Claim 11

The system of claim 4 , wherein said first sub-pool forms the unused memory entries as a block of individually contiguous entries chained together in a link.

Claim 12

The system of claim 4 , wherein said second sub-pool is a hashed table having a size chosen to be a prime number equal to or greater than seven.

Claim 15

The method of claim 11 , wherein said first sub-pool is a hashed table having a pool of the allocated memory entries.

Claim 16

The method of claim 11 , wherein said second sub-pool is a circularly linked-list having a pool of unused memory entries.

Claim 17

The method of claim 11 , wherein said adding said memory entry includes updating a current pointer of the first sub-pool to point to said memory entry.

Claim 18

The method of claim 11 , wherein said updating said second sub-pool includes updating a start address and a number of remaining entries in said second sub-pool.

Claim 19

The method of claim 11 , wherein said removing said requested memory entry includes appropriately reconnecting memory entry links for said first sub-pool.

Claim 20

The method of claim 11 , wherein said re-inserting said de-registered memory entry includes re-inserting the de-registered memory in an appropriate place in said second sub-pool.

Claim 21

The method of claim 17 , wherein said re-inserting said de-registered memory entry further includes appropriately connecting next entry pointers.

Claim 24

A computer system comprising: a processor; a memory controller coupled to said processor; a system memory coupled to said memory controller; a plurality of channel drivers to enable transfer of data between said system memory and input/output devices connected to the computer system; and a memory management system to manage memory associated with said plurality of channel drivers, the memory management system comprising; a memory entry pool including a plurality of entries to translate virtual memory addresses to physical memory addresses, the memory entry pool including; a first sub-pool comprising unallocated ones of the plurality of entries, a next pointer used as a starting point for searches to find a next available block of unallocated entries to be allocated; and a second sub-pool comprising allocated ones of the plurality of entries, the allocated entries not being available for the memory registration request.

Claim 25

A computer system comprising: a processor; a memory controller coupled to said processor; a system memory coupled to said memory controller; a plurality of channel drivers to enable transfer of data between said system memory and input/output devices connected to the computer system; and a memory management system to manage memory associated with said plurality of channel drivers, the memory management system comprising; a memory entry pool including a plurality of entries to translate virtual memory addresses to physical memory addresses, the memory entry pool including; a first sub-pool comprising unallocated ones of the plurality of entries, a next pointer used as a starting point for searches to find a next available block of unallocated entries to be allocated; and a second sub-pool comprising allocated ones of the plurality of entries, the allocated entries not being available for the memory registration request.

Claim 26

The computer system of claim 20 , wherein said computer system is used as a network server.

Claim 27

The memory management system of claim 20 wherein the memory entry pool comprises TPT records in a Translation and Protection Table.

Claim 28

The memory management system of claim 22 wherein the Translation and Protection Table is common to and is managed for the plurality of channel drivers.

Claim 29

The memory management system of claim 20 wherein the first sub-pool is configured as a circular linked list of records, each record representing a contiguous block of unallocated memory entries.

Claim 30

The memory management system of claim 20 wherein the first sub-pool includes a first pointer to point to a next one of the records, each record representing unallocated entries to be evaluated in response to receiving the memory registration request.

Claim 31

The memory management system of claim 20 wherein the second sub-pool is configured as a hashed table of records, each record representing a contiguous block of allocated memory entries.

Claim 32

The memory management system of claim 20 including a no-bias first-fit scheme to manage the first pool.