Erase method for nonvolatile semiconductor memory device

Claim 2

An erase method for a nonvolatile semiconductor memory device having electrically erasable and programmable floating gate field-effect transistors arranged in a matrix form so as to form a memory cell array, each memory cell having a control gate, a drain and a source, a plurality of word lines connected to the control gates of memory cells in each row, and a plurality of bit lines connected to the drains of memory cells in each column, the memory cell array being divided into a plurality of blocks including the memory cells of a plurality of rows and a plurality of columns, the sources of the memory cells in each block being commonly connected, and the memory cells in each block being commonly connected, and the memory cells in each block being connected together in a NOR type form, said erase method executing an erase operation in blocks and comprising: executing, for the memory cells connected to one word line in a certain block, an erase pulse application for erasing information, a first verify operation for verifying a threshold voltage shift due to the erase pulse application and a second verify operation for verifying whether excessive erasure has occurred due to the erase pulse application; and executing a soft program operation for the memory cell after the second verify operation and before application of an erase pulse to a next word line when a memory cell that has undergone excessive erasure is found by the second verify operation, said pulse application, said first verify operation, and said second verify operation being executed word line by word line in the block.

Claim 3

The erase method as claimed in claim 1 , wherein a target range of threshold voltages of each memory cell in an erased state is set lower than a lower limit value of threshold voltages in a written state, the first verify operation verifies that the threshold voltages of the memory cells connected to the word line are equal to or lower than an upper limit value of the target range, and the second verify operation verifies that the threshold voltages of the memory cells connected to the word line are equal to or higher than a lower limit value of the target range.

Claim 4

The erase method as claimed in claim 2 , wherein the soft program operation is executed by means of channel hot electrons.

Claim 5

The erase method as claimed in claim 2 , wherein a voltage applied to the control gate of a memory cell in the soft program operation is same in polarity as and smaller in value than a voltage applied to the control gate of the memory cell during a write operation, and a voltage applied to the drain of the memory cell in the soft program operation is substantially identical to a voltage applied to the drain of the memory cell in the write operation.

Claim 6

The erase method as claimed in claim 1 , wherein the erase pulse application includes applying a first voltage to the sources of a certain block, applying a second voltage to one word line selected from the plurality of word lines of the block, and applying a third voltage to non-selected word lines of the block, to thereby extract electrons from the floating gate to the source of each memory cell connected to the selected word line.

Claim 7

The erase method as claimed in claim 5 , wherein the first voltage is a positive voltage, the second voltage is a negative voltage and the third voltage is a reference voltage.

Claim 8

The erase method as claimed in claim 1 , wherein each memory cell constituted of the floating gate field-effect transistor has a triple well structure in which a P-well that provides a channel region is formed via an N-well on a P-type semiconductor substrate, and the erase pulse application includes applying a first voltage to the source and the P-well of a certain block, applying a second voltage to one word line selected from the plurality of word lines of the block, and applying a third voltage to non-selected word lines of the block, to thereby extract electrons from the floating gate to the channel region of each memory cell connected to the selected word line.

Claim 9

The erase method as claimed in claim 7 , wherein the first voltage is a positive voltage, the second voltage is a negative voltage and the third voltage is a reference voltage or a positive voltage lower than the first voltage.

Claim 10

An erase method for a nonvolatile semiconductor memory device having electrically erasable and programmable floating gate filed-effect transistors arranged in a matrix form so as to form a memory cell array, each memory cell having a control gate, a drain and a source, a plurality of word lines connected to the control gates of memory cells in each row, and a plurality of bit lines connected to the drains of memory cells in each column, the memory cell array being divided into a plurality of blocks including the memory cells of a plurality of rows and a plurality of columns, each block being divided into a plurality of segments with respect to a row direction, each bit line consisting of a main bit line and a plurality of sub-bit lines connected to the main bit line via a respective select transistor, the sub-bit lines being connected to the drains of the memory cells included in the corresponding segments, the sources of the memory cells in each block being commonly connected, and the memory cells in each block being connected together in a NOR type form, said erase method executing an erase operation in blocks and comprising: executing, for the memory cells connected to one word line in each segment of a certain block, an erase pulse application for erasing information, a first verify operation for verifying a threshold voltage shift due to the erase pulse application and a second verify operation for verifying whether excessive erasure has occurred due to the erase pulse application; and executing a soft program operation for the memory cell after the second verify operation and before application of an erase pulse to a next word line when a memory cell that has undergone excessive erasure is found by the second verify operation, said erase pulse application, said first verify operation, said second verify operation, and said soft program operation being executed in the plurality of segments of the block in parallel, and said erase pulse application, said first verify operation being executed word line by word line in each segment of the block.

Claim 11

An erase method for a nonvolatile semiconductor memory device having electrically erasable and programmable floating gate filed-effect transistors arranged in a matrix form so as to form a memory cell array, each memory cell having a control gate, a drain and a source, a plurality of word lines connected to the control gates of memory cells in each row, and a plurality of bit lines connected to the drains of memory cells in each column, the memory cell array being divided into a plurality of blocks including the memory cells of a plurality of rows and a plurality of columns, each block being divided into a plurality of segments with respect to a row direction, each bit line consisting of a main bit line and a plurality of sub-bit lines connected to the main bit line via a respective select transistor, the sub-bit lines being connected to the drains of the memory cells included in the corresponding segments, the sources of the memory cells in each block being commonly connected, and the memory cells in each block being connected together in a NOR type form, said erase method executing an erase operation in blocks and comprising: executing, for the memory cells connected to one word line in each segment of a certain block, an erase pulse application for erasing information, a first verify operation for verifying a threshold voltage shift due to the erase pulse application and a second verify operation for verifying whether excessive erasure has occurred due to the erase pulse application; and executing a soft program operation for the memory cell after the second verify operation and before application of an erase pulse to a next word line when a memory cell that has undergone excessive erasure is found by the second verify operation, said erase pulse application, said first verify operation, said second verify operation, and said soft program operation being executed in the plurality of segments of the block in parallel, and said erase pulse application, said first verify operation being executed word line by word line in each segment of the block.

Claim 12

The erase method as claimed in claim 9 , wherein a target range of threshold voltages of each memory cell in an erased state is set lower than a lower limit value of threshold voltages in a written state, the first verify operation verifies that the threshold voltages of the memory cells connected to the word line are equal to or lower than an upper limit value of the target range, and the second verify operation verifies that the threshold voltages of the memory cells connected to the word line are equal to or higher than a lower limit value of the target range.

Claim 13

The erase method as claimed in claim 9 , wherein the first verify operation and the second verify operation for the memory cells connected to the selected word line are executed by turning on the select transistors for the sub-bit lines included in the segment through which the selected word line extends while turning off the select transistors for the sub-bit lines included in remaining segments.