Serial MRAM device

Claim 2

A resistive semiconductor device, comprising: a semiconductor substrate; a plurality of magnetic memory storage cells disposed over the substrate, each storage cell including a first end and a second end, the storage cells being coupled in series to one another so that a first end of one of the storage cells is coupled to a second end of an adjacent one of the storage cells; and a plurality of transistors, a respective one of the transistors being coupled in parallel to each memory storage cell, the transistors coupled in series to one another, the transistors being adapted to control access to the memory storage cells, wherein the transistors comprise depletion devices.

Claim 3

The resistive semiconductor device according to claim 1 , wherein the cells are magnetic random-access memory (MRAM) cells.

Claim 4

The resistive semiconductor device according to claim 2 , wherein the magnetic memory storage cells comprise magnetic stacks, the magnetic stacks including a tunnel junction, wherein a logic state is storable in each magnetic stack.

Claim 5

The resistive semiconductor device according to claim 3 , wherein data stored in each memory storage cell is accessed by turning on at least one of the transistors.

Claim 6

The resistive semiconductor device according to claim 4 , further comprising a plurality of wordlines, bitlines and digitlines proximate the memory storage cells, wherein the magnetic stacks are not coupled directly to the wordlines, bitlines and digitlines.

Claim 7

The resistive semiconductor device according to claim 5 , wherein current may be passed bidirectionally through the tunnel junctions.

Claim 8

The resistive semiconductor device according to claim 1 , further comprising a plurality of vias coupling at least one side of each magnetic stack to an active area.

Claim 9

The resistive semiconductor device according to claim 7 , wherein the active area is continuous and enables each of the plurality of transistors.

Claim 10

A magnetic random-access memory (MRAM) semiconductor device, comprising: a semiconductor substrate; a first transistor having a gate, a first source/drain region and second source/drain region disposed on the substrate; a second transistor having a gate, a first source/drain region and a second source/drain region, the second transistor first source/drain region being coupled to the first transistor second source/drain region; a first magnetic stack having a first end and a second end, the first magnetic stack first end being coupled to the first transistor first source/drain region by a first via extending upwardly from the first transistor first source/region and abutting the first end of the first magnetic stack; a second magnetic stack having a first end and a second end, the second magnetic stack first end being coupled to the second transistor second source/drain region by a second via extending upwardly from the second transistor second source/drain region and abutting the first end of the second magnetic stack; a first conductor coupled to and extending between the second end of the first magnetic stack and the second end of the second magnetic stack; a third via extending upwardly from the first transistor second source/drain region to the first conductor; a first metal plate disposed over and abutting both the first via and the first magnetic stack first end; and a second metal plate disposed over and abutting both the second via and the second magnetic stack first end, the second metal plate being separate from the first metal plate.

Claim 11

A magnetic random-access memory (MRAM) semiconductor device, comprising: a semiconductor substrate; a first transistor having a gate, a first source/drain region and second source/drain region disposed on the substrate; a second transistor having a gate, a first source/drain region and a second source/drain region, the second transistor first source/drain region being coupled to the first transistor second source/drain region; a first magnetic stack having a first end and a second end, the first magnetic stack first end being coupled to the first transistor first source/drain region by a first via extending upwardly from the first transistor first source/region and abutting the first end of the first magnetic stack; a second magnetic stack having a first end and a second end, the second magnetic stack first end being coupled to the second transistor second source/drain region by a second via extending upwardly from the second transistor second source/drain region and abutting the first end of the second magnetic stack; a first conductor coupled to and extending between the second end of the first magnetic stack and the second end of the second magnetic stack; a third via extending upwardly from the first transistor second source/drain region to the first conductor; a first metal plate disposed over and abutting both the first via and the first magnetic stack first end; and a second metal plate disposed over and abutting both the second via and the second magnetic stack first end, the second metal plate being separate from the first metal plate.

Claim 12

The MRAM semiconductor device according to claim 9 , further comprising: a first wordline coupled to the first transistor gate; a second wordline coupled to the second transistor gate; and a bitline coupled to the first transistor first source/drain region.

Claim 13

The MRAM semiconductor device according to claim 10 , further comprising: a third transistor having a gate, a first source/drain region and a second source/drain region, the third transistor first source/drain region being coupled to the second transistor second source/drain region, the third transistor gate being coupled to a third wordline; a fourth transistor having a gate, a first source/drain region and a second source/drain region, the fourth transistor first source/drain region being coupled to the third transistor second source/drain region, the fourth transistor gate bring coupled to a fourth wordline; a third magnetic stack having a first end and a second end, the third magnetic stack first end being coupled to the second via; a fourth magnetic stack having a first end and a second end, the fourth magnetic stack first end being coupled to the fourth transistor second source/drain region by a fourth via; a second conductor coupled to and extending between the second end of the third magnetic stack and the second end of the fourth magnetic stack; and a fifth via extending upwardly from the third transistor second source/drain region to the second conductor; a third metal plate disposed over and abutting both the fourth via and the fourth magnetic stack first end, wherein the second metal plate is disposed over and abuts the third magnetic stack first end; and a ground node coupled to the fourth transistor second source/drain region.

Claim 14

The MRAM semiconductor device according to claim 11 , further comprising a select switch coupled between the bitline and the first transistor first source/drain region.

Claim 15

The MRAM semiconductor device according to claim 11 , further comprising a select switch coupled between the ground node and the fourth transistor second source/drain region.

Claim 16

The MRAM semiconductor device according to claim 11 , wherein the first, second, third and fourth transistors comprise depletion devices.

Claim 17

The MRAM semiconductor device according to claim 11 , wherein each magnetic stack includes a tunnel junction, wherein the tunnel junctions are not directly coupled to the bitline or wordlines.

Claim 20

The method according to claim 16 , further comprising disposing wordlines, bitlines and digitlines proximate the magnetic memory storage cells, wherein the wordlines, bitlines and digitlines are not directly coupled to the magnetic memory storage cells.

Claim 21

The method according to claim 16 , further comprising coupling each magnetic memory storage cell to a single active area.

Claim 22

A magnetic random access memory (MRAM) device, comprising: a semiconductor region having a first doped region, a second doped region, a third doped region, a fourth doped region and a fifth doped region formed therein, the fifth doped region being coupled to a ground; a first gate disposed above a portion of the semiconductor region between the first and second doped regions, the first gate being coupled to a first wordline; a second gate disposed above a portion of the semiconductor region between the second and third doped regions, the second gate being coupled to a second wordline; a single first via extending upwardly from the first doped region, the first via having an upper end; a first magnetic tunnel junction (MTJ) stack having a first end abutting the upper end of the first via; a second MTJ stack disposed proximate the first MTJ; a first conductor disposed below and coupling the first MTJ stack to the second MTJ stack; a single second via extending downwardly from the first conductor to contact the second doped region; a single third via having an upper end extending upwardly from the third doped region, wherein the third via upper end abuts the second MTJ stack; a first metal plate disposed above and abutting both the first via upper end and the first MTJ stack; a second metal plate disposed above and abutting both the third via upper end and the second MTJ stack; a third gate disposed above a portion of the semiconductor region between the third and fourth doped regions, the third gate being coupled to a third wordline; a fourth gate disposed above a portion of the semiconductor region between the fourth and fifth doped regions, the fourth gate being coupled to a fourth wordline; a third MTJ stack abutting the third via upper end, wherein the second metal plate is disposed above and abuts the third MTJ stack; a fourth MTJ stack disposed proximate the third MTJ; a second conductor disposed below and coupling the third MTJ stack to the and fourth MTJ stack; a single fourth via extending downwardly from the second conductor to contact the fourth doped region; a single fifth via having an upper end extending upwardly from the fifth doped region, wherein the fifth via upper end abuts the fourth MTJ stack; and a third metal plate disposed above and abutting both the fifth via upper end and the fourth MTJ stack.

Claim 23

A magnetic random access memory (MRAM) device, comprising: a semiconductor region having a first doped region, a second doped region, a third doped region, a fourth doped region and a fifth doped region formed therein, the fifth doped region being coupled to a ground; a first gate disposed above a portion of the semiconductor region between the first and second doped regions, the first gate being coupled to a first wordline; a second gate disposed above a portion of the semiconductor region between the second and third doped regions, the second gate being coupled to a second wordline; a single first via extending upwardly from the first doped region, the first via having an upper end; a first magnetic tunnel junction (MTJ) stack having a first end abutting the upper end of the first via; a second MTJ stack disposed proximate the first MTJ; a first conductor disposed below and coupling the first MTJ stack to the second MTJ stack; a single second via extending downwardly from the first conductor to contact the second doped region; a single third via having an upper end extending upwardly from the third doped region, wherein the third via upper end abuts the second MTJ stack; a first metal plate disposed above and abutting both the first via upper end and the first MTJ stack; a second metal plate disposed above and abutting both the third via upper end and the second MTJ stack; a third gate disposed above a portion of the semiconductor region between the third and fourth doped regions, the third gate being coupled to a third wordline; a fourth gate disposed above a portion of the semiconductor region between the fourth and fifth doped regions, the fourth gate being coupled to a fourth wordline; a third MTJ stack abutting the third via upper end, wherein the second metal plate is disposed above and abuts the third MTJ stack; a fourth MTJ stack disposed proximate the third MTJ; a second conductor disposed below and coupling the third MTJ stack to the and fourth MTJ stack; a single fourth via extending downwardly from the second conductor to contact the fourth doped region; a single fifth via having an upper end extending upwardly from the fifth doped region, wherein the fifth via upper end abuts the fourth MTJ stack; and a third metal plate disposed above and abutting both the fifth via upper end and the fourth MTJ stack.

Claim 24

The MRAM device according to claim 19 , wherein the first gate, a portion of the first doped region and a portion of the second doped region comprise a depletion device; wherein the second gate, a portion of the second doped region and a portion of the third doped region comprise a depletion device, wherein the third gate, a portion of the third doped region and a portion of the fourth doped region comprise a depletion device; and wherein the fourth gate, a portion of the fourth doped region and a portion of the fifth doped region comprise a depletion device.

Claim 25

The MRAM device according to claim 19 , further comprising: a sixth doped region formed in the semiconductor region proximate the first doped region; a fifth gate disposed above a portion of the semiconductor region between the first and sixth doped regions; and a sixth via having an upper end extending upwardly from the sixth doped region, the sixth via upper end abutting a bitline.