Non-volatile memory and method of non-volatile memory programming

Claim 2

A non-volatile memory, comprising: a plurality of word lines, a plurality of bit lines, a plurality of memory elements having stored information corresponding to electric charges accumulated at floating gates at intersections of said plurality of word lines and plurality of bit lines, said memory elements electrically performing operations to write and erase said stored information, and a write control circuit to control the electric charges accumulated at said floating gates by performing a verify operation, after performing a write operation in a prescribed write quantity on said memory elements, wherein said write control circuit carries out one or more search write operations to determine whether at least one of said memory elements includes an erratic cell, wherein said one or more search write operations are set to a different write quantity than said prescribed write quantity at a time of start of writing.

Claim 3

The non-volatile memory according to claim 1 , wherein: said write quantity is set based on at least one of a voltage level and a duration of writing, and said prescribed write quantity is set according to a voltage and a length of time that will make variation of threshold voltages of said memory elements substantially constant, and a quantity of search writing by a plurality of said search write operation is set to match said prescribed write quantity.

Claim 4

The non-volatile memory according to claim 1 , wherein said different write quantity is a variation in threshold voltage which is different from a variation in threshold voltage corresponding to said prescribed write quantity.

Claim 5

The non-volatile memory according to claim 1 , wherein said one or more search write operations include applying at least one search write pulse which is smaller in duration than subsequent write pulses applied during said write operation.

Claim 6

The non-volatile memory according to claim 4 wherein said at least one search write pulse applied during said one or more search write operations has a voltage level equal to a voltage level of subsequent write pulses applied during said write operation.

Claim 7

The non-volatile memory according to claim 4 , wherein said at least one search write pulse applied during said one or more search write operations has a voltage level which is lower than a voltage level of subsequent write pulses applied during said write operation.

Claim 8

The non-volatile memory according to claim 4 , wherein the write pulses applied during said write operation have progressively higher voltage levels, and wherein said at least one search write pulse applied during said one or more search write operations has a voltage level which is lower than voltage levels of all the write pulses applied during said write operation.

Claim 9

A non-volatile memory, comprising: a plurality of word lines; a plurality of bit lines; a plurality of memory elements having stored information corresponding to electric charges accumulated at floating gates at intersections of said plurality of word lines and plurality of bit lines, and electrically performing operations to write and erase said stored information; and a write control circuit to control the electric charges accumulated at said floating gates by performing a verify operation, after performing a write operation in a prescribed write quantity on said memory elements, wherein said write control circuit carries out one or more search write operations, set to a different write quantity than said prescribed write quantity at the time of start of writing, and verify operations corresponding thereto, wherein said different write quantity is set according to a product of a voltage level and a duration of writing, and said prescribed write quantity is set according to a voltage and a length of time that will make variations of threshold voltages of said memory elements substantially constant, and wherein a quantity of search writing by a plurality of said search write operations is set to match said prescribed write quantity, and wherein said memory elements have four-value information matching the quantity of electric charges accumulated at said floating gates.

Claim 10

A non-volatile memory, comprising: a plurality of word lines; a plurality of bit lines; a plurality of memory elements having stored information corresponding to electric charges accumulated at floating gates at intersections of said plurality of word lines and plurality of bit lines, and electrically performing operations to write and erase said stored information; and a write control circuit to control the electric charges accumulated at said floating gates by performing a verify operation, after performing a write operation in a prescribed write quantity on said memory elements, wherein said write control circuit carries out one or more search write operations, set to a different write quantity than said prescribed write quantity at the time of start of writing, and verify operations corresponding thereto, wherein said different write quantity is set according to a product of a voltage level and a duration of writing, and said prescribed write quantity is set according to a voltage and a length of time that will make variations of threshold voltages of said memory elements substantially constant, and wherein a quantity of search writing by a plurality of said search write operations is set to match said prescribed write quantity, and wherein said memory elements have four-value information matching the quantity of electric charges accumulated at said floating gates.

Claim 11

The non-volatile memory according to claim 8 , wherein: a write parameter is increased according to a number of times of writing such that the variation of said threshold voltage matching each write operation is kept substantially constant.

Claim 12

The non-volatile memory according to claim 9 , wherein: said search write operation has a smaller write duration than the write operations matching said prescribed write quantity.

Claim 13

The non-volatile memory according to claim 10 , wherein: said write parameter is write duration, which is increased while keeping a write voltage constant compared with a preceding write operation.

Claim 14

The non-volatile memory according to claim 10 , wherein: said write parameter is write duration.

Claim 15

A non-volatile memory comprising: a memory cell which stores information corresponding to charges accumulated at a floating gate of said cell; and a write control unit which controls the charges accumulated at said floating gate, said write control unit performing an operation to determine whether said memory cell is an erratic cell, wherein said write control circuit applies a set of write pulses to said memory cell, and wherein said operation includes: counting a number of write pulses required to accumulate a voltage in said memory cell which lies in a target range of voltages, said target range of voltages corresponding to said stored information; and determining that said memory cell is an erratic cell if the number of write pulses required to accumulate said voltage is fewer than a predetermined number.

Claim 16

A non-volatile memory comprising: a memory cell which stores information corresponding to charges accumulated at a floating gate of said cell; and a write control unit which controls the charges accumulated at said floating gate, said write control unit performing an operation to determine whether said memory cell is an erratic cell, wherein said write control circuit applies a set of write pulses to said memory cell, and wherein said operation includes: counting a number of write pulses required to accumulate a voltage in said memory cell which lies in a target range of voltages, said target range of voltages corresponding to said stored information; and determining that said memory cell is an erratic cell if the number of write pulses required to accumulate said voltage is fewer than a predetermined number.

Claim 17

The non-volatile memory according to claim 13 , wherein said number of write pulses have a same voltage level.

Claim 18

A non-volatile memory, comprising: a plurality of word lines; a plurality of bit lines; a plurality of memory element arranged at intersections of said plurality of word lines and said plurality of bit lines, each of said memory elements having a floating gate which accumulates electric charges corresponding to stored information; and a write control circuit which performs a write operation, including a first phase and a second phase, said write control circuit supplying one or more search write pulses to at least one of said memory elements in said first phase to determine whether said memory element includes an erratic cell.

Claim 19

A non-volatile memory, comprising: a plurality of word lines; a plurality of bit lines; a plurality of memory element arranged at intersections of said plurality of word lines and said plurality of bit lines, each of said memory elements having a floating gate which accumulates electric charges corresponding to stored information; and a write control circuit which performs a write operation, including a first phase and a second phase, said write control circuit supplying one or more search write pulses to at least one of said memory elements in said first phase to determine whether said memory element includes an erratic cell.

Claim 20

The non-volatile memory according to claim 15 , wherein said write control circuit supplies one or more write pulses to said memory element in said second phase so that said memory element will acquire said stored information, said one or more write pulses applied in said second phase being longer in duration than each said search write pulse.

Claim 21

The non-volatile memory according to claim 16 , wherein said search write pulses are formed to generate a smaller write quantity than a write quantity of the write pulses supplied in said second phase.

Claim 22

The non-volatile memory according to claim 17 , wherein said write quantity is a variation in threshold voltage generated in the memory cell.

Claim 23

The non-volatile memory according to claim 16 , wherein: said one or more search write pulses supplied during said first to a write quantity set based on at least one of a voltage level and a duration of writing, and said one or more write pulses supplied during said second phase correspond to a prescribed write quantity which is based on at least one of a voltage and a length of time that will make variations of threshold voltages of said memory elements substantially constant, and a total write quantity of said one or more search write pulses is set to match said prescribed write quantity.

Claim 24

The non-volatile memory according to claim 19 , wherein said write quantity is smaller than said prescribed write quantity.

Claim 25

The non-volatile memory according to claim 16 , wherein: said one or more search write pulses supplied during said first phase correspond to a write quantity, said write quantity being a variation in threshold voltage generated in the memory cell; and said one or more write pulses supplied during said second phase correspond to a prescribed write quantity, said prescribed write quantity being controlled so that a write parameter is increased to match a number of times of writing such that a variation of said threshold voltage matching each write operation is kept substantially constant.

Claim 26

The non-volatile memory according to claim 21 , wherein: said search write operation has a smaller write duration than the write operations matching said prescribed write quantity.

Claim 27

The non-volatile memory according to claim 22 wherein: said write parameter is write duration, which is increased while keeping a write voltage constant compared with a preceding write operation.

Claim 28

The non-volatile memory according to claim 22 , wherein: said write parameter is write duration.

Claim 29

The non-volatile memory according to claim 15 , wherein said memory elements store information of a plurality of bits.