US6522583B2
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US
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Nonvolatile semiconductor memory
Assignee: Kioxia Corp
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Filing: 2001-05-21
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Granted: 2003-02-18
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Expires: 2021-05-21
Abstract
Abstract A drain-side select gate line is set to VSG1 (>VDD) capable of sufficiently transferring VDD (time t1). Since all word lines in the selected block are set to Vread, VDD is applied to the channels of all memory cells in the cell units. After this, the drain-side select gate line is set to VSG2, and a program potential Vpgm is applied to the selected word line (times t2 to t3). Since VSG2 is sufficiently low, all drain-side select gate transistors are kept off, and the channel potentials of memory cells in all cell units are boosted. After this, since the drain-side select gate line is set to VSG3, the channel of the selected memory cell is set to 0V (time t4).
Inventors
- 👤 Kazushige Kanda
- 👤 Hiroshi Nakamura
- 👤 Koji Hosono
- 👤 Tamio Ikehashi
- 👤 Kenichi Imamiya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 02:54
CPC Classifications
G; G11; G11C; G11C17/00; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/04; G11C16/0483
Claims Analysis
Total Claims: 53
Claim 1
Independent Claim
73 words
A nonvolatile semiconductor memory comprising: at least one memory cell; and a select gate transistor connected between a bit line and said at least one memory cell, wherein write operation is performed during continuous first, second, and third periods, and when gate potentials of said select gate transistor during the first, second, and third periods are represented by first, second, and third potentials, respectively, a relationship given by first potential>third potential>second potential holds.
Claim 2
Dependent Claim
73 words
A nonvolatile semiconductor memory comprising: at least one memory cell; and a select gate transistor connected between a bit line and said at least one memory cell, wherein write operation is performed during continuous first, second, and third periods, and when gate potentials of said select gate transistor during the first, second, and third periods are represented by first, second, and third potentials, respectively, a relationship given by first potential>third potential>second potential holds.
Claim 3
Dependent Claim
76 words
A nonvolatile semiconductor memory comprising: at least one memory cell; and two select gate transistors respectively connected to two terminals of said at least one memory cell, wherein write operation is performed during continuous first, second, and third periods, and when gate potentials of one of said two select gate transistors during the first, second, and third periods are represented by first, second, and third potentials, respectively, a relationship given by first potential>third potential>second potential holds.
Claim 4
Dependent Claim
76 words
A nonvolatile semiconductor memory comprising: at least one memory cell; and two select gate transistors respectively connected to two terminals of said at least one memory cell, wherein write operation is performed during continuous first, second, and third periods, and when gate potentials of one of said two select gate transistors during the first, second, and third periods are represented by first, second, and third potentials, respectively, a relationship given by first potential>third potential>second potential holds.
Claim 5
Dependent Claim
46 words
The memory according to claim 1 , wherein the first period is a period when a potential corresponding to program data or a predetermined potential independent of the program data is applied to a channel of said at least one memory cell as an initial potential.
Claim 6
Dependent Claim
46 words
The memory according to claim 1 , wherein the second period is a period during which said select gate transistor is cut off, a program potential is applied to a selected word line, and a channel potential of said at least one memory cell is boosted.
Claim 7
Dependent Claim
74 words
The memory according to claim 1 , wherein the third period is a period during which if the bit line has a fourth potential, the fourth potential is transferred to a channel of said at least one memory cell through said select gate transistor, and if the bit line has a fifth potential, said select gate transistor is kept cut off, and a channel potential of said at least one memory cell is maintained.
Claim 8
Dependent Claim
24 words
The memory according to claim 1 , wherein the second period is a period during which said select gate transistor is kept cut off.
Claim 9
Dependent Claim
102 words
The memory according to claim 1 , wherein the third period includes a period during which if the bit line has a fourth potential, the fourth potential is transferred to a channel of said at least one memory cell through said select gate transistor, and if the bit line has a fifth potential, said select gate transistor is kept cut off and a channel potential of said at least one memory cell is maintained, and a period during which a program potential is applied to a selected word line and the channel potential of said at least one memory cell is boosted.
Claim 10
Dependent Claim
54 words
The memory according to claim 2 , wherein the second period is a period during which one of said select gate transistors is cut off and a predetermined potential independent of a program potential is applied to a channel of said at least one memory cell through the other of said select gate transistors.
Claim 11
Dependent Claim
96 words
A nonvolatile semiconductor memory, comprising: at least one memory cell; a first select gate transistor connected between a bit line and said at least one memory cell; and a second select gate transistor connected between a source line and said at least one memory cell, wherein write operation is performed during continuous first, second, third, and fourth periods, and when gate potentials of said first select gate transistor during the first, second, third, and fourth periods are represented by first, second, third, and fourth potentials, respectively, a relationship given by second potential>fourth potential>third potential≧first potential holds.
Claim 12
Dependent Claim
96 words
A nonvolatile semiconductor memory, comprising: at least one memory cell; a first select gate transistor connected between a bit line and said at least one memory cell; and a second select gate transistor connected between a source line and said at least one memory cell, wherein write operation is performed during continuous first, second, third, and fourth periods, and when gate potentials of said first select gate transistor during the first, second, third, and fourth periods are represented by first, second, third, and fourth potentials, respectively, a relationship given by second potential>fourth potential>third potential≧first potential holds.
Claim 13
Dependent Claim
55 words
The memory according to claim 9 , wherein the first period is a period during which said first select gate transistor is cut off and a predetermined potential independent of a program potential is applied from the source line to a channel of said at least one memory cell through said second select gate transistor.
Claim 14
Dependent Claim
66 words
The memory according to claim 9 , wherein the second period is a period during which said second select gate transistor is cut off and a potential corresponding to program data or a predetermined potential independent of the program data is applied from the bit line to a channel of said at least one memory cell through said first select gate transistor as an initial potential.
Claim 15
Dependent Claim
49 words
The memory according to claim 9 , wherein the third period is a period during which said first and second select gate transistors are cut off, a program potential is applied to a selected word line, and a channel potential of said at least one memory cell is boosted.
Claim 16
Dependent Claim
76 words
The memory according to claim 9 , wherein the fourth period is a period during which if the bit line has a fifth potential, the fifth potential is transferred to a channel of said at least one memory cell through said first select gate transistor, and if the bit line has a sixth potential, said first select gate transistor is kept cut off and a channel potential of said at least one memory cell is maintained.
Claim 17
Dependent Claim
27 words
The memory according to claim 9 , wherein the third period is a period during which said first and second select gate transistors are kept cut off.
Claim 18
Dependent Claim
104 words
The memory according to claim 9 , wherein the fourth period includes a period during which if the bit line has a fifth potential, the fifth potential is transferred to a channel of said at least one memory cell through said first select gate transistor, and if the bit line has a sixth potential, said first select gate transistor is kept cut off and a channel potential of said at least one memory cell is maintained, and a period during which a program potential is applied to a selected word line and the channel potential of said at least one memory cell is boosted.
Claim 19
Dependent Claim
178 words
A nonvolatile semiconductor memory comprising: at least one memory cell; a select gate transistor connected between a bit line and said at least one memory cell; and a control circuit for setting a gate potential of said select gate transistor to a first potential during a first period for applying an initial potential to a channel of said at least one memory cell, setting the gate potential of said select gate transistor to a second potential during a second period for boosting a channel potential of said at least one memory cell, and setting the gate potential of said select gate transistor to a third potential during a third period for if the bit line has a fourth potential, transferring the fourth potential to the channel of said at least one memory cell, and if the bit line has a fifth potential, maintaining the channel potential of said at least one memory cell, wherein the first, second, and third periods are continuous, and the first, second, and third potentials have a relationship given by first potential>third potential>second potential.
Claim 20
Dependent Claim
178 words
A nonvolatile semiconductor memory comprising: at least one memory cell; a select gate transistor connected between a bit line and said at least one memory cell; and a control circuit for setting a gate potential of said select gate transistor to a first potential during a first period for applying an initial potential to a channel of said at least one memory cell, setting the gate potential of said select gate transistor to a second potential during a second period for boosting a channel potential of said at least one memory cell, and setting the gate potential of said select gate transistor to a third potential during a third period for if the bit line has a fourth potential, transferring the fourth potential to the channel of said at least one memory cell, and if the bit line has a fifth potential, maintaining the channel potential of said at least one memory cell, wherein the first, second, and third periods are continuous, and the first, second, and third potentials have a relationship given by first potential>third potential>second potential.
Claim 21
Dependent Claim
184 words
A nonvolatile semiconductor memory comprising: at least one memory cell; two select gate transistors respectively connected to two terminals of said at least one memory cell; and a control circuit for setting a gate potential of one of said select gate transistors to a first potential during a first period for applying an initial potential to a channel of said at least one memory cell, setting the gate potential of one of said select gate transistors to a second potential during a second period for boosting a channel potential of said at least one memory cell, and setting the gate potential of one of said select gate transistors to a third potential during a third period for if the bit line has a fourth potential, transferring the fourth potential to the channel of said at least one memory cell, and if the bit line has a fifth potential, maintaining the channel potential of said at least one memory cell, wherein the first, second, and third periods are continuous, and the first, second, and third potentials have a relationship given by first potential>third potential>second potential.
Claim 22
Dependent Claim
184 words
A nonvolatile semiconductor memory comprising: at least one memory cell; two select gate transistors respectively connected to two terminals of said at least one memory cell; and a control circuit for setting a gate potential of one of said select gate transistors to a first potential during a first period for applying an initial potential to a channel of said at least one memory cell, setting the gate potential of one of said select gate transistors to a second potential during a second period for boosting a channel potential of said at least one memory cell, and setting the gate potential of one of said select gate transistors to a third potential during a third period for if the bit line has a fourth potential, transferring the fourth potential to the channel of said at least one memory cell, and if the bit line has a fifth potential, maintaining the channel potential of said at least one memory cell, wherein the first, second, and third periods are continuous, and the first, second, and third potentials have a relationship given by first potential>third potential>second potential.
Claim 23
Dependent Claim
186 words
A nonvolatile semiconductor memory comprising: at least one memory cell; a select gate transistor connected between a bit line and said at least one memory cell; and a control circuit for setting a gate potential of said select gate transistor to a first potential during a first period for applying an initial potential to a channel of said at least one memory cell, setting the gate potential of said select gate transistor to a second potential during a second period for cutting off said select gate transistor, and setting the gate potential of said select gate transistor to a third potential during a third period for if the bit line has a fourth potential, transferring the fourth potential to the channel of said at least one memory cell, and if the bit line has a fifth potential, maintaining a channel potential of said at least one memory cell and then boosting the channel potential of said at least one memory cell, wherein the first, second, and third periods are continuous, and the first, second, and third potentials have a relationship given by first potential>third potential>second potential.
Claim 24
Dependent Claim
186 words
A nonvolatile semiconductor memory comprising: at least one memory cell; a select gate transistor connected between a bit line and said at least one memory cell; and a control circuit for setting a gate potential of said select gate transistor to a first potential during a first period for applying an initial potential to a channel of said at least one memory cell, setting the gate potential of said select gate transistor to a second potential during a second period for cutting off said select gate transistor, and setting the gate potential of said select gate transistor to a third potential during a third period for if the bit line has a fourth potential, transferring the fourth potential to the channel of said at least one memory cell, and if the bit line has a fifth potential, maintaining a channel potential of said at least one memory cell and then boosting the channel potential of said at least one memory cell, wherein the first, second, and third periods are continuous, and the first, second, and third potentials have a relationship given by first potential>third potential>second potential.
Claim 25
Dependent Claim
194 words
A nonvolatile semiconductor memory comprising: at least one memory cell; two select gate transistors respectively connected to two terminals of said at least one memory cell; and a control circuit for setting a gate potential of one of said select gate transistors to a first potential during a first period for applying an initial potential to a channel of said at least one memory cell, setting the gate potential of one of said select gate transistors to a second potential during a second period for cutting off one of said select gate transistors, and setting the gate potential of one of said select gate transistors to a third potential during a third period for if the bit line has a fourth potential, transferring the fourth potential to the channel of said at least one memory cell, and if the bit line has a fifth potential, maintaining a channel potential of said at least one memory cell and then boosting the channel potential of said at least one memory cell, wherein the first, second, and third periods are continuous, and the first, second, and third potentials have a relationship given by first potential>third potential>second potential.
Claim 26
Dependent Claim
194 words
A nonvolatile semiconductor memory comprising: at least one memory cell; two select gate transistors respectively connected to two terminals of said at least one memory cell; and a control circuit for setting a gate potential of one of said select gate transistors to a first potential during a first period for applying an initial potential to a channel of said at least one memory cell, setting the gate potential of one of said select gate transistors to a second potential during a second period for cutting off one of said select gate transistors, and setting the gate potential of one of said select gate transistors to a third potential during a third period for if the bit line has a fourth potential, transferring the fourth potential to the channel of said at least one memory cell, and if the bit line has a fifth potential, maintaining a channel potential of said at least one memory cell and then boosting the channel potential of said at least one memory cell, wherein the first, second, and third periods are continuous, and the first, second, and third potentials have a relationship given by first potential>third potential>second potential.
Claim 27
Dependent Claim
202 words
A nonvolatile semiconductor memory comprising: at least one memory cell; two select gate transistors respectively connected to two terminals of said at least one memory cell; and a control circuit for setting a gate potential of one of said select gate transistors to a first potential, and then setting a gate potential of the other of said select gate transistors to the first potential during a first period for applying an initial potential to a channel of said at least one memory cell, setting the gate potential of one of said select gate transistors to a second potential during a second period for boosting a channel potential of said at least one memory cell, and setting the gate potential of one of said select gate transistors to a third potential during a third period for if the bit line has a fourth potential, transferring the fourth potential to the channel of said at least one memory cell, and if the bit line has a fifth potential, maintaining the channel potential of said at least one memory cell, wherein the first, second, and third periods are continuous, and the first, second, and third potentials have a relationship given by first potential>third potential>second potential.
Claim 28
Dependent Claim
202 words
A nonvolatile semiconductor memory comprising: at least one memory cell; two select gate transistors respectively connected to two terminals of said at least one memory cell; and a control circuit for setting a gate potential of one of said select gate transistors to a first potential, and then setting a gate potential of the other of said select gate transistors to the first potential during a first period for applying an initial potential to a channel of said at least one memory cell, setting the gate potential of one of said select gate transistors to a second potential during a second period for boosting a channel potential of said at least one memory cell, and setting the gate potential of one of said select gate transistors to a third potential during a third period for if the bit line has a fourth potential, transferring the fourth potential to the channel of said at least one memory cell, and if the bit line has a fifth potential, maintaining the channel potential of said at least one memory cell, wherein the first, second, and third periods are continuous, and the first, second, and third potentials have a relationship given by first potential>third potential>second potential.
Claim 29
Dependent Claim
212 words
A nonvolatile semiconductor memory comprising: at least one memory cell; two select gate transistors respectively connected to two terminals of said at least one memory cell; and a control circuit for setting a gate potential of one of said select gate transistors to a first potential, and then setting a gate potential of the other of said select gate transistors to the first potential during a first period for applying an initial potential to a channel of said at least one memory cell, setting the gate potential of one of said select gate transistors to a second potential during a second period for cutting off one of said select gate transistors, and setting the gate potential of one of said select gate transistors to a third potential during a third period for if the bit line has a fourth potential, transferring the fourth potential to the channel of said at least one memory cell, and if the bit line has a fifth potential, maintaining a channel potential of said at least one memory cell and then boosting the channel potential of said at least one memory cell, wherein the first, second, and third periods are continuous, and the first, second, and third potentials have a relationship given by first potential>third potential>second potential.
Claim 30
Dependent Claim
212 words
A nonvolatile semiconductor memory comprising: at least one memory cell; two select gate transistors respectively connected to two terminals of said at least one memory cell; and a control circuit for setting a gate potential of one of said select gate transistors to a first potential, and then setting a gate potential of the other of said select gate transistors to the first potential during a first period for applying an initial potential to a channel of said at least one memory cell, setting the gate potential of one of said select gate transistors to a second potential during a second period for cutting off one of said select gate transistors, and setting the gate potential of one of said select gate transistors to a third potential during a third period for if the bit line has a fourth potential, transferring the fourth potential to the channel of said at least one memory cell, and if the bit line has a fifth potential, maintaining a channel potential of said at least one memory cell and then boosting the channel potential of said at least one memory cell, wherein the first, second, and third periods are continuous, and the first, second, and third potentials have a relationship given by first potential>third potential>second potential.
Claim 31
Dependent Claim
99 words
The memory according to claim 20 , wherein when the gate potential of one of said select gate transistors is set to the first potential, a predetermined potential independent of program data is applied from a source line to said at least one memory cell through one of said select gate transistors, and when the gate potential of the other of said select gate transistors is set to the first potential, a potential corresponding to the program data is applied from a bit line to said at least one memory cell through the other of said select gate transistors.
Claim 32
Dependent Claim
99 words
The memory according to claim 21 , wherein when the gate potential of one of said select gate transistors is set to the first potential, a predetermined potential independent of program data is applied from a source line to said at least one memory cell through one of said select gate transistors, and when the gate potential of the other of said select gate transistors is set to the first potential, a potential corresponding to the program data is applied from a bit line to said at least one memory cell through the other of said select gate transistors.
Claim 33
Dependent Claim
99 words
The memory according to claim 20 , wherein when the gate potential of one of said select gate transistors is set to the first potential, a potential corresponding to program data is applied from a bit line to said at least one memory cell through one of said select gate transistors, and when the gate potential of the other of said select gate transistors is set to the first potential, a predetermined potential independent of the program data is applied from a source line to said at least one memory cell through the other of said select gate transistors.
Claim 34
Dependent Claim
99 words
The memory according to claim 21 , wherein when the gate potential of one of said select gate transistors is set to the first potential, a potential corresponding to program data is applied from a bit line to said at least one memory cell through one of said select gate transistors, and when the gate potential of the other of said select gate transistors is set to the first potential, a predetermined potential independent of the program data is applied from a source line to said at least one memory cell through the other of said select gate transistors.
Claim 35
Dependent Claim
44 words
The memory according to claim 3 , wherein the potential corresponding to the program data includes an internal power supply potential and ground potential, and the predetermined potential independent of the program data is a potential not less than the internal power supply potential.
Claim 36
Dependent Claim
44 words
The memory according to claim 11 , wherein the potential corresponding to the program data includes an internal power supply potential and ground potential, and the predetermined potential independent of the program data is a potential not less than the internal power supply potential.
Claim 37
Dependent Claim
23 words
The memory according to claim 1 , wherein the first potential has a value larger than that of an internal power supply potential.
Claim 38
Dependent Claim
23 words
The memory according to claim 2 , wherein the first potential has a value larger than that of an internal power supply potential.
Claim 39
Dependent Claim
23 words
The memory according to claim 9 , wherein the second potential has a value larger than that of an internal power supply potential.
Claim 40
Dependent Claim
33 words
The memory according to claim 1 , wherein the third potential is set to a value that can transfer a ground potential and cannot transfer an internal power supply potential or clamp potential.
Claim 41
Dependent Claim
33 words
The memory according to claim 2 , wherein the third potential is set to a value that can transfer a ground potential and cannot transfer an internal power supply potential or clamp potential.
Claim 42
Dependent Claim
33 words
The memory according to claim 9 , wherein the fourth potential is set to a value that can transfer a ground potential and cannot transfer an internal power supply potential or clamp potential.
Claim 43
Dependent Claim
50 words
The memory according to claim 1 , wherein during the first period, a word line of said at least one memory cell is set to a potential that turns on all of said at least one memory cell independently of a data state of said at least one memory cell.
Claim 44
Dependent Claim
50 words
The memory according to claim 2 , wherein during the first period, a word line of said at least one memory cell is set to a potential that turns on all of said at least one memory cell independently of a data state of said at least one memory cell.
Claim 45
Dependent Claim
75 words
A nonvolatile semiconductor memory comprising: at least one memory cell; and a select gate transistor connected between a bit line and said at least one memory cell, wherein at the start of write operation, a write inhibit potential is applied to a channel of said at least one memory cell independently of program data, and then, a potential corresponding to the program data is applied to the channel of said at least one memory cell.
Claim 46
Dependent Claim
75 words
A nonvolatile semiconductor memory comprising: at least one memory cell; and a select gate transistor connected between a bit line and said at least one memory cell, wherein at the start of write operation, a write inhibit potential is applied to a channel of said at least one memory cell independently of program data, and then, a potential corresponding to the program data is applied to the channel of said at least one memory cell.
Claim 47
Dependent Claim
50 words
The memory according to claim 36 , wherein when the program data represents write inhibition, the potential corresponding to the program data has a value smaller than that of the write inhibit potential applied to the channel of said at least one memory cell at the start of write operation.
Claim 48
Dependent Claim
35 words
The memory according to claim 36 , wherein a program potential is applied to a selected word line after the write inhibit potential is applied to the channel of said at least one memory cell.
Claim 49
Dependent Claim
79 words
A nonvolatile semiconductor memory comprising: a memory cell; and a select gate transistor connected between said memory cell and a source line, wherein write operation is performed during continuous first and second periods, and when gate potentials of said select gate transistor during the first and second periods are represented by first and second potentials, respectively, a relationship given by first potential>second potential holds, and during the second period, a program potential is applied to a selected word line.
Claim 50
Dependent Claim
79 words
A nonvolatile semiconductor memory comprising: a memory cell; and a select gate transistor connected between said memory cell and a source line, wherein write operation is performed during continuous first and second periods, and when gate potentials of said select gate transistor during the first and second periods are represented by first and second potentials, respectively, a relationship given by first potential>second potential holds, and during the second period, a program potential is applied to a selected word line.
Claim 51
Dependent Claim
87 words
A nonvolatile semiconductor memory comprising: at least one memory cell; two select gate transistors respectively connected to two terminals of said at least one memory cell, and a control circuit for supplying a first unselected potential to a bit line regardless of a state of said at least one memory cell when a program operation is started, and for supplying a second unselected potential or a selected potential to said bit line based on the state of said at least one memory cell during said program operation.
Claim 52
Dependent Claim
87 words
A nonvolatile semiconductor memory comprising: at least one memory cell; two select gate transistors respectively connected to two terminals of said at least one memory cell, and a control circuit for supplying a first unselected potential to a bit line regardless of a state of said at least one memory cell when a program operation is started, and for supplying a second unselected potential or a selected potential to said bit line based on the state of said at least one memory cell during said program operation.
Claim 53
Dependent Claim
19 words
The memory according to claim 40 , wherein said second unselected potential is higher than said first unselected potential.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 7.5 Years (Year 8) | 2010-02-17 | 2010-08-19 | 2011-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-02-17 | 2014-08-19 | 2015-02-18 | $7700.00 | Window Closed / Lapsed |