US6584006B2
Expired / Lapsed
US
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MRAM bit line word line architecture
Assignee: Polaris Innovations Ltd
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Filing: 2001-09-27
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Granted: 2003-06-24
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Expires: 2021-09-27
Abstract
Abstract A memory device comprising a plurality of bit lines and a plurality of word lines forming a cross-point array. A memory cell is located at each of the cross-points in the array. A bit decoder and word decoder are coupled to the bit lines and word lines, respectively. A first series of switch circuits are coupled to and located along the adjacent bit lines resulting in the array being divided into segments along the adjacent bit lines such that a shortened programming current path is provided which results in decreased resistance across the device.
Inventors
- 👤 Hans-Heinrich Viehmann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:24
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/02; G11C11/14; G11C11/15; G11C7/00; G11C7/12; G11C11/16; G11C7/18; G11C8/00; G11C8/08; G11C8/14
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
159 words
A memory device comprising: a plurality of bit lines; a plurality of word lines, the plurality of word lines forming a cross-point array with the plurality of bit lines; a plurality of memory cells, whereby one of the plurality of memory cells is located at each of the cross-points in the array; a bit decoder coupled to the bit lines, the bit decoder having current sources and current sinks coupled to the bit lines; a word decoder coupled to the word lines, the word decoder having current sources and current sinks coupled to the word lines; and a first series of switch circuits coupled to two adjacent bit lines, the first series of switch circuits located along the adjacent bit lines resulting in the array being divided into segments along the adjacent bit lines; whereby the memory cell at the corresponding cross-point is selected for writing when the corresponding bit and word lines are provided with a programming current.
Claim 2
Dependent Claim
159 words
A memory device comprising: a plurality of bit lines; a plurality of word lines, the plurality of word lines forming a cross-point array with the plurality of bit lines; a plurality of memory cells, whereby one of the plurality of memory cells is located at each of the cross-points in the array; a bit decoder coupled to the bit lines, the bit decoder having current sources and current sinks coupled to the bit lines; a word decoder coupled to the word lines, the word decoder having current sources and current sinks coupled to the word lines; and a first series of switch circuits coupled to two adjacent bit lines, the first series of switch circuits located along the adjacent bit lines resulting in the array being divided into segments along the adjacent bit lines; whereby the memory cell at the corresponding cross-point is selected for writing when the corresponding bit and word lines are provided with a programming current.
Claim 3
Dependent Claim
17 words
The device as in claim 1 wherein the device is a magnetic random access memory (MRAM) device.
Claim 4
Dependent Claim
13 words
The device as in claim 1 wherein the programming current is 5 milliamps.
Claim 5
Dependent Claim
31 words
The device as in claim 1 wherein the amount of programming current sent through each of the two adjacent bit lines is equal to about one half of the programming current.
Claim 6
Dependent Claim
53 words
The device as in claim 1 wherein the switch circuits are designed to allow less than the programming current to flow through each of the two adjacent bit lines resulting in none of the plurality of memory cells coupled to either of the adjacent bit lines within a segment being selected for writing.
Claim 7
Dependent Claim
47 words
The device as in claim 5 wherein each switch circuit is designed to allow the programming current to flow through either one of the two adjacent bit lines in a segment resulting in memory cell coupled to the bit line within a segment being selected for writing.
Claim 8
Dependent Claim
45 words
The device as in claim 1 wherein a second series of switch circuits are coupled to two adjacent word lines, the second series of switch circuits located along the adjacent word lines resulting in the array being divided into segments along the adjacent word lines.
Claim 9
Dependent Claim
31 words
The device as in claim 7 wherein the amount of programming current sent through each of the two adjacent word lines is equal to about one half of the programming current.
Claim 10
Dependent Claim
56 words
The device as in claim 7 wherein the second series of switch circuits are designed to allow less than the programming current to flow through each of the two adjacent word lines resulting in none of the plurality of memory cells coupled to either of the adjacent word lines within a segment being selected for writing.
Claim 11
Dependent Claim
52 words
The device as in claim 9 wherein each of the second series of switch circuit is designed to allow programming current to flow through either one of the two adjacent word lines in a segment resulting in the memory device coupled to the word line within a segment being selected for writing.
Claim 12
Dependent Claim
41 words
The device as in claim 7 wherein each of the first and second series of switch circuits comprises a series of transistors, each transistor connected to a control line whereby a signal is provided to turn the transistor on or off.
Claim 13
Dependent Claim
21 words
The device as in claim 11 wherein the series of transistors are turned on to switch the current path as desired.
Claim 14
Dependent Claim
22 words
The device as in claim 11 wherein a control signal to turn the series of transistors on originates at a control circuit.
Claim 15
Dependent Claim
15 words
The device as in claim 13 wherein the control circuit is located in the decoder.
Claim 16
Dependent Claim
21 words
The device as in claim 7 wherein the first and second series of switch circuits are located beneath the cross-point array.
Claim 17
Independent Claim
122 words
A method of selecting a memory cell in a cross-point array having a plurality of conductive lines, the array having switch circuits located along two adjacent conductive lines resulting in segments of the two adjacent conductive lines, the method comprising: selecting a memory cell for writing, the memory cell coupled to one of the two adjacent conductive lines in an associated segment; programming the switch circuits whereby the one of two adjacent conductive lines in the associated segment receives a programming current and a other of the two adjacent conductive lines in the associated segment receives no programming current; and programming the switch circuits whereby the two adjacent conductive lines in the other segments each receive a portion of the programming current.
Claim 18
Independent Claim
122 words
A method of selecting a memory cell in a cross-point array having a plurality of conductive lines, the array having switch circuits located along two adjacent conductive lines resulting in segments of the two adjacent conductive lines, the method comprising: selecting a memory cell for writing, the memory cell coupled to one of the two adjacent conductive lines in an associated segment; programming the switch circuits whereby the one of two adjacent conductive lines in the associated segment receives a programming current and a other of the two adjacent conductive lines in the associated segment receives no programming current; and programming the switch circuits whereby the two adjacent conductive lines in the other segments each receive a portion of the programming current.
Claim 19
Dependent Claim
17 words
The method of claim 16 wherein the switch circuits are switched by a series of control signals.
Claim 20
Dependent Claim
16 words
The method of claim 17 wherein the series of control signals originate at a control circuit.
Claim 21
Dependent Claim
20 words
The method of claim 16 wherein the portion of programming current is equal to about one-half of the programming current.
Claim 22
Dependent Claim
34 words
The method of claim 16 wherein the method further comprises providing programming current to a corresponding word line of the memory cell selected to allow data to be written to the selected memory cell.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-06-23 | 2006-12-23 | 2007-06-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-06-23 | 2010-12-23 | 2011-06-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-06-23 | 2014-12-23 | 2015-06-24 | $7700.00 | Window Closed / Lapsed |