US6645879B2
Expired / Lapsed
US
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Method of forming a silicon oxide layer of a semiconductor device and method of forming a wiring having the same
Assignee: Samsung Electronics Co Ltd
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Filing: 2002-08-08
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Granted: 2003-11-11
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Expires: 2022-08-08
Abstract
Abstract Disclosed are methods for forming a silicon oxide layer of a semiconductor device capable of insulating between fine conductive patterns without causing a process failure, and for forming a wiring having the silicon oxide layer. After forming conductive patterns on a semiconductor substrate, an anti-oxidation layer is sequentially formed on the conductive patterns and on the semiconductor substrate. The anti-oxidation layer prevents an oxidant from penetrating into the conductive patterns and the semiconductor substrate. A reflowable oxide layer is formed by coating a reflowable oxidizing material on the anti-oxidation layer while burying the conductive patterns. The silicon oxide layer is formed by thermally treating the reflowable oxide layer. Then, the silicon oxide layer filled between conductive patterns and the anti-oxidation layer exposed to the semiconductor substrate are etched so as to form a contact hole, thereby forming the wiring of the semiconductor device. Thus, a planar silicon oxide layer is formed between conductive patterns having a fine interval therebetween without creating a void. In addition, a metal layer pattern, which acts as a conductor in the conductive patterns, can be prevented from being oxidized when the silicon oxide layer is formed.
Inventors
- 👤 Eun-Kee Hong
- 👤 Ju-Bum Lee
- 👤 Ju-seon Goo
- 👤 Myeong-cheol Kim
- 👤 Hong-Gun Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 14:39
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6316; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6336; H10P52/00; H10P95/00; H10P95/06; H10W20/071; H10W20/074; H10W20/077; H10W20/092; H10W20/093; H10W20/097; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/0335; H10B12/30; H10B12/48; H10B12/482; Y; Y10; Y10S; Y10S438/00; Y10S438/935
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
98 words
A method for forming an insulating layer in a semiconductor device, the method comprising the steps of: i) forming a plurality of conductive patterns on a semiconductor substrate; ii) sequentially forming an anti-oxidation layer on the conductive patterns and on the semiconductor substrate for preventing an oxidant from penetrating into the conductive patterns and the semiconductor substrate; iii) forming a reflowable oxide layer by coating a reflowable oxide material on the conductive patterns having the anti-oxidation layer formed thereon while burying the conductive patterns; and iv) forming a silicon oxide layer by thermally treating the reflowable oxide layer.
Claim 2
Independent Claim
98 words
A method for forming an insulating layer in a semiconductor device, the method comprising the steps of: i) forming a plurality of conductive patterns on a semiconductor substrate; ii) sequentially forming an anti-oxidation layer on the conductive patterns and on the semiconductor substrate for preventing an oxidant from penetrating into the conductive patterns and the semiconductor substrate; iii) forming a reflowable oxide layer by coating a reflowable oxide material on the conductive patterns having the anti-oxidation layer formed thereon while burying the conductive patterns; and iv) forming a silicon oxide layer by thermally treating the reflowable oxide layer.
Claim 3
Dependent Claim
16 words
The method as claimed in claim 1 , wherein the anti-oxidation layer includes a nitride layer.
Claim 4
Dependent Claim
21 words
The method as claimed in claim 1 , wherein the anti-oxidation layer has a thickness of about 30 to 500 Å.
Claim 5
Dependent Claim
37 words
The method as claimed in claim 1 , wherein the anti-oxidation layer is formed through one of a low-pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, and an atmospheric-pressure chemical vapor deposition process.
Claim 6
Dependent Claim
25 words
The method as claimed in claim 1 , wherein the reflowable oxide layer is at least one of an SOG layer and a BPSG layer.
Claim 7
Dependent Claim
52 words
The method as claimed in claim 5 , wherein the SOG layer is thermally treated by a) pre-baking the SOG layer at a temperature range of about 40 to 450° C.; and b) performing a main baking process on the SOG layer at a temperature range of about 400 to 1000° C.
Claim 8
Dependent Claim
38 words
The method as claimed in claim 6 , wherein step b) is carried out for about 10 to 120 minutes in one of an oxygen atmosphere, a vapor atmosphere and a mixed gas atmosphere of oxygen and vapor.
Claim 9
Dependent Claim
43 words
The method as claimed in claim 5 , wherein the BPSG layer is thermally treated for about 10 to 120 minutes in an atmosphere including one of oxygen and vapor while maintaining a temperature in a range of about 600 to 900° C.
Claim 10
Dependent Claim
34 words
The method as claimed in claim 1 , wherein the conductive pattern includes a composite layer pattern having a metal layer pattern and a nitride layer pattern sequentially deposited on the metal layer pattern.
Claim 11
Dependent Claim
27 words
The method as claimed in claim 9 , wherein the nitride layer pattern is formed by patterning a nitride layer which is deposited through a PE-CVD process.
Claim 12
Dependent Claim
42 words
The method as claimed in claim 1 , further comprising the step of, after forming the silicon oxide layer, forming a contact hole for partially exposing the semiconductor substrate between the conductive patterns by using the conductive patterns as an aligning mask.
Claim 13
Dependent Claim
60 words
The method as claimed in claim 11 , wherein the contact hole is formed by etching a predetermined portion of the silicon oxide layer to expose sidewalls of the conductive layer patterns between conductive layer patterns and the anti-oxidation layer formed on the semiconductor substrate and anisotropically etching the anti-oxidation layer on the semiconductor substrate to expose the semiconductor substrate.
Claim 14
Dependent Claim
25 words
The method as claimed in claim 12 , wherein the etching process for the silicon oxide layer and the anti-oxidation layer is carried out in-situ.
Claim 15
Dependent Claim
30 words
The method as claimed in claim 1 , further comprising the step of forming a nitride layer spacer at sidewalls of the conductive patterns before the anti-oxidation layer is formed.
Claim 16
Independent Claim
193 words
A method for forming a wiring in a semiconductor device, the method comprising the steps of; i) forming an insulating layer including a plurality of first conductive patterns therein on a semiconductor substrate; ii) forming second conductive patterns on the insulating layer corresponding to upper portions of spaces formed between first conductive patterns; iii) sequentially forming an anti-oxidation layer on upper surfaces of the second conductive patterns and the insulating layer for preventing an oxidant from penetrating into the second conductive patterns and the insulating layer; iv) forming a reflowable oxide layer by coating a reflowable oxide material on the anti-oxidation layer while burying the second conductive patterns; v) forming a silicon oxide layer by thermally treating the reflowable oxide layer; vi) forming a preliminary contact hole for exposing the anti-oxidation layer formed on the insulating layer by anisotropically etching a predetermined portion of the silicon oxide layer; vii) anisotropically etching the anti-oxidation layer exposed to the upper surface of the insulating layer and the insulating layer, in sequence, thereby forming a contact hole for exposing an upper surface of the first conductive patterns; and viii) filling conductive materials in the contact hole.
Claim 17
Independent Claim
193 words
A method for forming a wiring in a semiconductor device, the method comprising the steps of; i) forming an insulating layer including a plurality of first conductive patterns therein on a semiconductor substrate; ii) forming second conductive patterns on the insulating layer corresponding to upper portions of spaces formed between first conductive patterns; iii) sequentially forming an anti-oxidation layer on upper surfaces of the second conductive patterns and the insulating layer for preventing an oxidant from penetrating into the second conductive patterns and the insulating layer; iv) forming a reflowable oxide layer by coating a reflowable oxide material on the anti-oxidation layer while burying the second conductive patterns; v) forming a silicon oxide layer by thermally treating the reflowable oxide layer; vi) forming a preliminary contact hole for exposing the anti-oxidation layer formed on the insulating layer by anisotropically etching a predetermined portion of the silicon oxide layer; vii) anisotropically etching the anti-oxidation layer exposed to the upper surface of the insulating layer and the insulating layer, in sequence, thereby forming a contact hole for exposing an upper surface of the first conductive patterns; and viii) filling conductive materials in the contact hole.
Claim 18
Dependent Claim
15 words
The method as claimed in claim 15 ,wherein the anti-oxidation layer is a nitride layer.
Claim 19
Dependent Claim
25 words
The method as claimed in claim 15 , wherein the reflowable oxide layer is at least one of an SOG layer and a BPSG layer.
Claim 20
Dependent Claim
52 words
The method as claimed in claim 17 , wherein the SOG layer is thermally treated by a) pre-baking the SOG layer at a temperature range of about 40 to 450° C.; and b) performing a main baking process on the SOG layer at a temperature range of about 400 to 1000° C.
Claim 21
Dependent Claim
43 words
The method as claimed in claim 17 , wherein the BPSG layer is thermally treated for about 10 to 120 minutes in an atmosphere including one of oxygen and vapor while maintaining a temperature at a range of about 600 to 900° C.
Claim 22
Dependent Claim
36 words
The method as claimed in claim 15 , wherein, after forming the silicon oxide layer, one of a chemical mechanical polishing process and an etch back process is carried out for planarizing the silicon oxide layer.
Claim 23
Dependent Claim
18 words
The method as claimed in claim 15 , wherein step vi) and step vii) are carried out in-situ.
Claim 24
Independent Claim
240 words
A method for forming a wiring in a semiconductor device, the method comprising the steps of; i) forming an insulating layer including a plurality of first conductive patterns therein on a semiconductor substrate; ii) forming second conductive patterns on the insulating layer corresponding to upper portions of spaces formed between first conductive patterns; iii) forming a nitride layer spacer at sidewalls of the second conductive patterns; iv) forming a first preliminary contact hole for exposing an upper surface of the first conductive patterns by performing an anisotropic etching process using the nitride layer spacer as an etching mask; v) sequentially forming an anti-oxidation layer on an upper surface of the second conductive pattern, an upper surface of the insulating layer, and a sidewall and a bottom surface of the first preliminary contact hole, for preventing an oxidant from penetrating thereto; vi) forming a reflowable oxide layer by coating a reflowable oxide material on the anti-oxidation layer while burying the first preliminary contact hole; vii) forming a silicon oxide layer by thermally treating the reflowable oxide layer; viii) forming a second preliminary contact hole by anisotropically etching a predetermined portion of the silicon oxide layer, thereby exposing the anti-oxidation layer formed on the bottom surface of the first preliminary contact hole; ix) etching the exposed anti-oxidation layer, thereby forming a contact hole for exposing the upper surface of the first conductive patterns; and x) filling conductive materials in the contact hole.
Claim 25
Independent Claim
240 words
A method for forming a wiring in a semiconductor device, the method comprising the steps of; i) forming an insulating layer including a plurality of first conductive patterns therein on a semiconductor substrate; ii) forming second conductive patterns on the insulating layer corresponding to upper portions of spaces formed between first conductive patterns; iii) forming a nitride layer spacer at sidewalls of the second conductive patterns; iv) forming a first preliminary contact hole for exposing an upper surface of the first conductive patterns by performing an anisotropic etching process using the nitride layer spacer as an etching mask; v) sequentially forming an anti-oxidation layer on an upper surface of the second conductive pattern, an upper surface of the insulating layer, and a sidewall and a bottom surface of the first preliminary contact hole, for preventing an oxidant from penetrating thereto; vi) forming a reflowable oxide layer by coating a reflowable oxide material on the anti-oxidation layer while burying the first preliminary contact hole; vii) forming a silicon oxide layer by thermally treating the reflowable oxide layer; viii) forming a second preliminary contact hole by anisotropically etching a predetermined portion of the silicon oxide layer, thereby exposing the anti-oxidation layer formed on the bottom surface of the first preliminary contact hole; ix) etching the exposed anti-oxidation layer, thereby forming a contact hole for exposing the upper surface of the first conductive patterns; and x) filling conductive materials in the contact hole.
Claim 26
Dependent Claim
16 words
The method as claimed in claim 22 , wherein the anti-oxidation layer includes a nitride layer.
Claim 27
Dependent Claim
25 words
The method as claimed in claim 22 , wherein the reflowable oxide layer is at least one of an SOG layer and a BPSG layer.
Claim 28
Dependent Claim
38 words
The method as claimed in claim 22 , wherein, after forming the silicon oxide layer, at least one of a chemical mechanical polishing process and an etch back process is carried out for planarizing the silicon oxide layer.
Claim 29
Dependent Claim
17 words
The method as claimed in claim 22 , wherein steps viii) and ix) are carried out in-situ.
References Cited (Backward Citations)
US6225236B1
Cited
US5879986A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2006-11-10 | 2007-05-12 | 2007-11-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-11-10 | 2011-05-12 | 2011-11-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-11-10 | 2015-05-12 | 2015-11-11 | $7700.00 | Window Closed / Lapsed |